PLL Circuit Phase Adjustment via Amplitude Amplification

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Solution Overview

Problem

The existing PLL circuit's accuracy in adjusting the phase of the output clock signal is insufficient, leading to reduced precision in detecting sensitivity signal components, which affects the accuracy of engine control and airbag operation in preventing automobile side slips.

Innovation Solution

A PLL circuit with a phase difference detection unit, control voltage generation unit, voltage control oscillator, frequency divider, and a control unit that amplifies the reference clock signal with an amplification factor based on the phase difference, allowing for precise phase adjustment of the output clock signal without increasing the frequency or using high-accuracy digital phase comparators.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the frequency of the reference clock signal is increased to improve phase adjustment accuracy, then the phase adjustment accuracy is improved, but the power consumption increases and the circuit complexity increases

Engineering Contradiction:

Improvephase adjustment accuracyVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The invention changes the parameter of the reference clock signal from frequency to amplitude. By amplifying the reference clock signal with an amplification factor according to the phase difference, the system achieves high phase adjustment accuracy without increasing the frequency, thus avoiding increased power consumption and circuit complexity associated with high-frequency operations

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If a high-accuracy digital phase comparator is used to improve phase detection accuracy, then the phase detection accuracy is improved, but the device complexity and cost increase

Engineering Contradiction:

Improvephase detection accuracyVSAvoidcircuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The invention changes the detection parameter from phase difference magnitude to amplitude variation. The phase difference detection unit detects the amplitude of the reference clock signal at specific timing based on the feedback clock signal, and the control unit generates control signals based on this amplitude information. This approach achieves high phase detection accuracy using simple comparison logic without requiring complex high-accuracy phase comparators

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The invention replaces the traditional mechanical/analog phase comparison mechanism with a digital amplitude-based detection system. Instead of using complex analog phase detectors or high-precision digital phase comparators, the system uses simple digital logic to detect amplitude variations of the reference clock signal, achieving the same phase detection function with significantly reduced circuit complexity

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If the amplification factor is increased to improve detection sensitivity, then the detection sensitivity is improved, but the noise amplification increases

Engineering Contradiction:

Improvedetection sensitivityVSAvoidnoise amplification

Core Design Contradiction:

Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The invention uses periodic sampling of the reference clock signal amplitude at specific timing points determined by the feedback clock signal. By detecting amplitude only at these specific periodic intervals rather than continuously amplifying the entire signal, the system achieves high detection sensitivity while limiting noise amplification to only the necessary measurement moments

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The system uses the existing clock signals (reference clock and feedback clock) to generate the detection timing and control signals without requiring external high-frequency signals or additional complex timing circuits. The feedback clock signal itself provides the timing reference for amplitude detection, making the system self-sufficient and avoiding the need for additional high-frequency components that would amplify noise

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS10148273B2PLL circuit, semiconductor device, electronic control unit, and control method of PLL circuit

Publication Date: 2018.12.04 RENESAS ELECTRONICS CORP

AI summary

According to one embodiment, a PLL circuit includes: a digital phase comparator that captures an instantaneous value of a reference clock signal, which is a digital since wave, in synchronization with a feedback clock signal, and detects a phase difference between the reference clock signal and the feedback clock signal based on the captured instantaneous value; a control voltage generation unit that generates a control voltage according to the phase difference; a voltage control oscillator that generates an output clock signal having a frequency according to the control voltage; a frequency divider that divides a frequency of the output clock signal to generate the feedback clock signal; and a control unit that amplifies the reference clock signal to be supplied to the digital phase comparator with an amplification factor according to the phase difference.