PLL Clock Resampling in the Analog Domain to Reduce Jitter
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuits face challenges in reducing jitter, which is caused by noise in the digital domain and power supply fluctuations, making it difficult to maintain accurate clock signals.
Innovation Solution
The proposed solution involves a PLL circuit design that includes a digital voltage circuit, a clock resampling circuit, an analog circuit feedback loop, and an output voltage circuit. This design resamples clock signals from the digital domain into the analog domain using flip-flops, minimizing jitter by transferring signals from a noisy digital voltage domain to a cleaner analog domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signals are processed in the digital domain with high-frequency switching, then digital circuit operation is achieved, but noise and jitter increase
Solution Approach 1:
The patent introduces an analog domain as an intermediary between digital clock signals and the PLL circuit. Clock signals from the digital domain are transferred to the analog domain through level shifters and maintained there throughout PLL processing. This intermediary analog domain isolates the PLL from digital switching noise while preserving clock signal integrity, resolving the contradiction between digital operation and noise reduction.
2Adaptability or versatility
If signals are transferred between different voltage domains, then voltage level matching is achieved, but additional noise is introduced
Solution Approach 1:
The patent performs voltage domain conversion in advance, before signals enter the PLL circuit. Level shifters convert digital voltage levels to analog voltage levels at the input stage, and the signals remain in the analog domain throughout subsequent processing. This preliminary conversion eliminates the need for repeated voltage domain transitions within the PLL, preventing additional noise generation while maintaining voltage compatibility.
3Productivity
If the PLL loop integrates noise present in the input signal, then frequency multiplication is achieved, but output jitter increases
Solution Approach 1:
The patent extracts and removes digital switching noise from the clock signal path before it enters the PLL integration loop. By maintaining clock signals in the analog domain and using analog dividers instead of digital ones, the system prevents digital noise from being captured and amplified by the PLL's integration function. This extraction of harmful digital noise components allows frequency multiplication while minimizing output jitter.
Data Source
AI summary
A method and apparatus for reducing jitter in a phase-locked loop (PLL). Clock signals provided to the PLL are resampled into the voltage domain of the VCO in the PLL rather than being merely level shifted into that voltage domain or input directly from digital domain clock dividers as in the prior art. The resampling is done with flip-flops in the analog domain using a faster synchronous clock in each case, and results in cleaner clock edges being presented to the PLL than those provided by the digital circuitry alone. A divided input clock signal is resampled using the undivided input clock, while a divided feedback clock signal is resampled using the feedback clock signal itself, i.e., the output of the VCO in the PLL. This removes jitter caused by the processing of clock signals in the digital voltage domain and thus reduces the jitter in the output signal.