Self-Configuring PLL Bandwidth Control for Constant Damping
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Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in maintaining stability and adjusting loop bandwidth across varying reference frequencies, requiring knowledge of the reference frequency, which is often unknown, leading to instability and overshoot.
Innovation Solution
A phase-locked loop design that includes a frequency detector and a state machine to automatically adjust the loop bandwidth and maintain a constant damping factor, using digital-to-analog converters to adjust capacitances and charge-pump current based on detected frequencies, allowing the PLL to operate effectively without knowing the reference frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the loop bandwidth is adjusted manually for different reference frequencies, then the damping factor can be maintained, but the device requires knowledge of the reference frequency which is often unknown
Solution Approach 1:
The PLL circuit automatically detects the reference frequency and adjusts its own loop bandwidth and damping factor without external intervention. The system measures FREF using a frequency detector and state machine, then self-configures the charge-pump current and integrating capacitance to maintain optimal performance across varying reference frequencies.
Solution Approach 2:
The circuit dynamically changes key parameters (charge-pump current magnitude and integrating capacitance value) based on the detected reference frequency. By adjusting these parameters proportionally to FREF, the loop bandwidth scales automatically while maintaining a constant damping factor, resolving the contradiction between adaptability and complexity.
2Adaptability or versatility
If the reference frequency varies over a large range, then the PLL can serve diverse applications, but maintaining constant damping factor becomes difficult without knowing FREF
Solution Approach 1:
The system uses a frequency detector and state machine to measure the reference frequency and feeds this information back to automatically adjust the loop bandwidth. This closed-loop feedback mechanism ensures that the damping factor remains constant even as the reference frequency varies across a wide range from 2 MHz to 30 MHz.
Solution Approach 2:
The PLL transitions from a static design with fixed parameters to a dynamic system where the charge-pump current and integrating capacitance are continuously adjusted based on the detected reference frequency. This dynamic adaptation allows the circuit to maintain optimal damping characteristics across diverse operating conditions.
3Device complexity
If the loop bandwidth is fixed, then the circuit design is simplified, but the PLL cannot adapt to varying reference frequencies leading to instability
Solution Approach 1:
The system performs preliminary detection of the reference frequency before locking the PLL. The frequency detector and state machine measure FREF in advance and pre-configure the appropriate charge-pump current and capacitance values, allowing the loop bandwidth to be properly scaled before the PLL begins operation, thus maintaining both simplicity and adaptability.
Data Source
AI summary
A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.