PLL Loop Bandwidth Switching for Faster Relocking After Cycle Slips
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Solution Overview
Problem
Phase locked loops (PLLs) experience prolonged relocking times due to cycle slips between input and feedback clock signals, which is undesirable in environments like telecommunication networks where stability and speed are critical.
Innovation Solution
Incorporating a cycle slip detector that increases the loop bandwidth of the PLL by enhancing the bandwidth of the low-pass filter, allowing for faster relocking by detecting cycle slips and adjusting the loop bandwidth accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the loop bandwidth of the PLL is increased to reduce relocking time, then the relocking speed improves, but the jitter performance and frequency stability deteriorate
Solution Approach 1:
The patent dynamically adjusts the loop bandwidth of the PLL based on the detected state. When a cycle slip is detected, the loop bandwidth is increased to accelerate relocking. Once relocking is achieved, the loop bandwidth is reduced to restore optimal jitter performance and frequency stability. This dynamic adjustment resolves the contradiction by allowing high bandwidth only when needed for speed, and low bandwidth when stability is prioritized.
Solution Approach 2:
The patent changes the loop bandwidth parameter in response to detected cycle slips. By temporarily increasing the loop bandwidth parameter during cycle slip events and then restoring it to normal values after relocking, the system achieves fast relocking without permanently sacrificing frequency stability and jitter performance.
2Loss of time
If a cycle slip detector is added to detect cycle slips and adjust loop bandwidth, then the relocking time is reduced, but the device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the cycle slip detector monitors the phase detector output for cycle slip conditions, triggers bandwidth adjustment when slips are detected, and restores normal operation after relocking. This feedback-based approach automates the bandwidth adjustment process, reducing manual intervention while managing the added complexity through systematic control.
Solution Approach 2:
The PLL system performs self-diagnosis and self-adjustment by detecting its own cycle slip conditions and automatically modifying its loop bandwidth parameter. The cycle slip detector enables the system to identify when relocking is needed and triggers the appropriate bandwidth changes without external control, allowing the system to service itself during transient disturbances.
Data Source
AI summary
A phase locked loop (PLL) includes a phase detector, a first low-pass filter, an oscillator, a feedback divider and a cycle slip detector. The cycle slip detector is operable to detect at a first time instance, a cycle slip between an input clock and a feedback clock of the PLL. Upon detection of the cycle slip, the cycle slip detector is operable to increase a loop BW of the PLL. As a result, faster relocking of the PLL is achieved upon occurrence of an abrupt and large frequency difference between the input clock and the feedback clock.