PLL Bandwidth Calibration Using Integrated Phase Error Signals
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Solution Overview
Problem
Existing calibration systems for phase-locked loops (PLLs) and frequency synthesizers face challenges in accurately and efficiently calibrating bandwidth variations due to process and temperature changes, leading to mismatches between analog and digital transfer functions, which affect modulation accuracy and spectral emissions.
Innovation Solution
A method and system that detect an error signal generated by the PLL in response to a stimulus, integrate it, and compare it to a nominal value to adjust the PLL bandwidth, using error-detection circuitry, arithmetic units, and calibration charge pumps to modify components such as the charge pump or loop filter, thereby maintaining bandwidth accuracy with minimal power and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional calibration schemes using high-resolution ADCs and amplifiers are used to measure loop-filter tuning voltage, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts only the essential information needed for calibration by directly detecting the phase error signal from the PLL, eliminating the need for complex ADCs and amplifiers. The phase error signal inherently contains the bandwidth calibration information, so no additional measurement circuitry is required.
Solution Approach 2:
The PLL's own phase error signal is used for calibration purposes, turning an internal signal that would otherwise be discarded into a useful calibration reference. This self-service approach eliminates external measurement equipment and reduces system complexity.
2Measurement precision
If bandwidth of the frequency synthesizer is extended using digital pre-emphasis techniques, then modulation accuracy is improved, but mismatch between analog and digital transfer functions worsens
Solution Approach 1:
The patent implements a feedback mechanism where the phase error signal is continuously monitored and used to adjust the charge pump current, thereby dynamically compensating for bandwidth variations. This closed-loop approach ensures that the analog and digital transfer functions remain matched across different operating conditions.
Solution Approach 2:
The patent changes the charge pump current parameter based on the detected phase error signal to compensate for bandwidth variations. By adjusting this key parameter, the system adapts to different operating conditions and maintains accurate modulation performance.
3Stability of the object's composition
If existing calibration methods are used to compensate for VCO gain variation, then bandwidth stability is improved, but power consumption and silicon area increase
Solution Approach 1:
The patent merges the calibration function with the existing PLL operation by using the phase error signal that is already present during normal operation. This eliminates the need for separate calibration circuits and operations, reducing both power consumption and silicon area while maintaining bandwidth stability.
Solution Approach 2:
The phase error signal serves multiple functions: it is used for both normal PLL operation and for bandwidth calibration. This multi-functionality reduces the need for dedicated calibration hardware, thereby lowering power consumption and area requirements.
Data Source
AI summary
A method for calibrating a bandwidth of a phase-locked loop begins with detecting an error signal generated by the phase-locked loop in response to a stimulus signal. The difference between the integral of the error signal and a nominal value thereof is computed, and the bandwidth of the phase-locked loop is adjusted based on the computed difference.