PLL Bandwidth Ramping to Reduce Overclocking Frequency Spikes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in maintaining stability and preventing malfunction during overclocking, as they struggle to respond to changes in reference clock frequencies while avoiding large frequency spikes, which can lead to improper device function and overheating.
Innovation Solution
The PLL adjusts its loop bandwidth incrementally in response to frequency changes by using a phase-frequency detector, lock detector, delay circuit, bandwidth control counter, adjustable charge pump, low-pass filter, and voltage-controlled oscillator to gradually change the charge pump current, reducing frequency spikes through multiple incremental bandwidth steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a small bandwidth is used for the PLL during overclocking, then the frequency ramp ratio requirement is met, but large changes in bandwidth cause large frequency spikes that fail frequency spike requirements
Solution Approach 1:
The patent segments the bandwidth adjustment process into multiple incremental steps. Instead of making a single large bandwidth change, the system divides the total bandwidth adjustment into N smaller steps, where each step changes the bandwidth by a fraction (1/N) of the total required change. This segmentation allows the PLL to meet frequency ramp ratio requirements while minimizing frequency spikes at each step.
Solution Approach 2:
The patent implements dynamic bandwidth adjustment by making the PLL bandwidth adaptive during the overclocking process. The bandwidth is dynamically changed in multiple stages as the frequency transitions, allowing the system to optimize performance at each frequency stage rather than using a fixed small bandwidth throughout the entire transition.
2Productivity
If a large bandwidth is used for the PLL after overclocking, then normal operation performance is achieved, but the transition causes large frequency spikes
Solution Approach 1:
The patent applies segmentation to the bandwidth increase process after overclocking. The transition from small overclocking bandwidth to large normal operation bandwidth is divided into multiple incremental steps. Each step increases the bandwidth by a controlled amount, preventing large frequency spikes while ultimately achieving the desired normal operation performance.
Solution Approach 2:
The patent prepares for the bandwidth increase by first establishing a stable locked state at the new frequency with small bandwidth. This preliminary action ensures the PLL is properly locked before initiating the multi-step bandwidth increase process, preventing frequency spikes during the transition to normal operation bandwidth.
3Loss of time
If the PLL bandwidth is changed rapidly to meet frequency changes, then response time is improved, but stability is compromised due to frequency spikes
Solution Approach 1:
The patent implements a dynamic bandwidth adjustment strategy that adapts to the PLL's locking status. The system rapidly changes frequency references but controls bandwidth changes dynamically - using small bandwidth during frequency transitions to maintain stability, then incrementally increasing bandwidth once locked to improve response time without causing frequency spikes.
Solution Approach 2:
The patent maintains continuous useful action by keeping the PLL in a locked state throughout the bandwidth adjustment process. The incremental bandwidth changes are performed while the PLL remains locked, ensuring continuous frequency generation without interruption or instability, thus maintaining both response time and stability.
Data Source
AI summary
In a phase-locked loop, a desired change in frequency is indicated. The phase-locked loop locks to the new frequency and a loop bandwidth of the phase-locked loop is changed. In changing the loop bandwidth, a frequency adjustment signal to a voltage-controlled oscillator may include a voltage spike. The voltage spike is reduced by detecting a lock when the reference clock and a feedback clock reach a same frequency, then waiting for a time delay after the detecting the lock, and adjusting a current level of a charge pump pulse by an incremental amount to achieve a fractional portion of a new loop bandwidth. The charge pump pulse is filtered to generate the frequency adjustment signal and the frequency spike reduction process is repeated until the new loop bandwidth is achieved.