PLL Bandwidth Selection for Low-Kvco Display Driver Clocks
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuits in display drivers face instability due to increased gain Kvco at high control voltages, requiring manual bandwidth selection and additional external pins, and fail to accurately reflect control voltage changes in oscillation frequency.
Innovation Solution
A phase-locked loop circuit that generates two clock signals with a 1 unit interval (UI) phase difference, using a bandwidth selection circuit to automatically select frequency bands based on interval-specific delay times, allowing the voltage-controlled oscillator to operate with a lower gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gain Kvco of the voltage-controlled oscillator is increased to broaden the operating frequency range, then the frequency range is expanded, but the output becomes susceptible to instability and noise
Solution Approach 1:
The patent segments the frequency tuning range into multiple discrete bands by dividing the capacitor array into different groups (first capacitor group, second capacitor group, etc.). Each group corresponds to a specific frequency band, allowing the VCO to operate at lower gain within each band while still achieving broad overall frequency coverage through band selection.
Solution Approach 2:
The patent dynamically selects the appropriate capacitor group based on the desired frequency band, enabling the VCO to adapt its operating characteristics. By switching between different capacitor groups rather than continuously adjusting capacitance, the system maintains optimal gain and stability for each frequency range.
2Adaptability or versatility
If manual bandwidth selection with additional external pins is used to expand the operating frequency range, then the frequency range is broadened, but the device complexity increases
Solution Approach 1:
The patent implements self-service by automatically determining the appropriate frequency band and selecting the corresponding capacitor group without requiring external intervention. The bandwidth selection circuit autonomously configures the VCO based on input parameters, eliminating the need for additional external pins and manual bandwidth selection.
Solution Approach 2:
The patent creates a universal bandwidth selection circuit that can automatically adapt to different frequency requirements using a standardized control mechanism. This multi-functional approach allows the same circuit architecture to handle various frequency bands without requiring separate control pins or complex external configuration.
3Speed
If the voltage-controlled oscillator operates at high control voltage ranges, then the oscillation frequency increases, but the Kvco decreases and the oscillation frequency does not properly reflect the control voltage
Solution Approach 1:
The patent applies local quality by optimizing the capacitor configuration for each frequency band. Different capacitor groups are designed with specific capacitance values tailored to their respective frequency ranges, ensuring that the VCO maintains accurate and linear frequency control characteristics within each local band rather than attempting a single uniform design across the entire frequency range.
Data Source
AI summary
A phase-locked loop circuit includes a voltage-controlled oscillator configured to output a variable clock signal with an oscillation frequency based on a control voltage, and a bandwidth selection circuit configured to output a binary code value supplied to the voltage-controlled oscillator. The voltage-controlled oscillator outputs the variable clock signal based on a bandwidth selected according to the binary code value. Accordingly, the voltage-controlled oscillator may operate with a lower gain.