PLL Bandwidth Calibration Using Offset-Compensated Phase Steps
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Solution Overview
Problem
Phase-locked loop (PLL) dynamics measurement is challenging due to variations in gains and offsets, leading to inaccuracies in determining the locations and adjustments of poles and zeros, especially in the presence of phase offsets and nonlinearities.
Innovation Solution
The method involves temporarily shutting off the proportional path in a PLL, introducing phase steps of opposite polarities, and measuring the time-to-zero crossing to accurately determine the natural frequency and damping coefficient, allowing for adjustments to achieve target values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If phase steps are introduced to measure PLL bandwidth, then measurement capability is enabled, but measurement precision deteriorates due to phase offsets and nonlinearities
Solution Approach 1:
The patent extracts the measurement function from the normal PLL operation by introducing test phase steps that temporarily disrupt the locked state. This allows separate measurement of PLL characteristics without requiring the PLL to maintain its normal operating condition, thereby enabling measurement capability while managing the precision issues through controlled disruption.
Solution Approach 2:
The patent changes the phase parameter by introducing controlled phase steps of known magnitude into the PLL input. By varying the phase parameter in a controlled manner and measuring the system's response, the bandwidth can be determined despite the presence of offsets and nonlinearities that would otherwise prevent accurate measurement.
2Adaptability or versatility
If PLL operates with variable gains and offsets, then adaptability is improved, but measurement precision deteriorates
Solution Approach 1:
The patent performs preliminary characterization of the PLL by measuring its response to phase steps under different operating conditions. This preliminary action captures the effects of variable gains and offsets, allowing the system to adapt to changing conditions while maintaining measurement precision through pre-characterized compensation data.
Solution Approach 2:
The patent uses feedback from the measured phase response to iteratively refine the determination of pole and zero locations. By continuously comparing the actual response with expected responses and adjusting the model accordingly, the system maintains measurement precision even as gains and offsets vary due to temperature, supply voltage, or manufacturing tolerances.
3Stability of the object's composition
If proportional path is active during measurement, then PLL stability is maintained, but parameter measurement accuracy deteriorates
Solution Approach 1:
The patent employs periodic phase step interruptions to measure PLL parameters. The proportional path remains active during normal operation, but periodic test signals are introduced to probe the system response. This periodic action allows the PLL to maintain stability during normal operation while enabling accurate parameter measurement during the brief measurement intervals.
Solution Approach 2:
The patent segments the measurement process into distinct phases: normal locked operation with proportional path active, and measurement intervals where phase steps are introduced. This segmentation allows the proportional path to maintain stability during normal operation while enabling precise measurement during dedicated measurement windows, separating the conflicting requirements in time.
Data Source
AI summary
A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter.