PLL Coarse-Tune Bandwidth Control for Faster Stable Locking
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Solution Overview
Problem
Conventional dual-loop PLL circuits suffer from slow locking response speed due to a fixed and limited bandwidth of the coarse tune low-pass filter, which hinders quick and accurate frequency and phase locking.
Innovation Solution
The PLL circuit incorporates a coarse tune low-pass filter module with a dynamically narrowing bandwidth, utilizing a first and second VCO gain and a mixer to generate oscillation signals, and a bandwidth controller with a timer and second low-pass filter to adjust the filter bandwidth, enabling rapid frequency adjustment and precise locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a fixed and limited bandwidth of coarse tune low-pass filter is used, then stability is improved, but locking response speed deteriorates
Solution Approach 1:
The patent applies the dynamics principle by transforming the fixed bandwidth of the coarse tune low-pass filter into a dynamically adjustable bandwidth. The filter bandwidth is varied over time: initially set to a larger value to enable fast frequency acquisition and locking response, then gradually reduced to a smaller value to achieve fine frequency tuning and high stability. This time-varying bandwidth adjustment resolves the contradiction between fast response and stability by adapting the filter characteristics to different stages of the locking process.
2Stability of the object's composition
If a large resistor and large capacitor are used in coarse tune loop, then a pole at very low frequency is generated improving stability, but device complexity and size increase
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bandwidth parameter of the coarse tune low-pass filter instead of using fixed large resistor and capacitor values. The bandwidth is controlled to be large during initial locking to ensure stability, then reduced during fine tuning. This parameter adjustment approach achieves the desired stability without requiring physically large components, thereby reducing circuit complexity and size while maintaining the pole at low frequency effect.
Data Source
AI summary
A phase lock loop (PLL) circuit having a phase frequency detector (PFD), a coarse tune low-pass filter module, a voltage control oscillation (VCO) module and a feedback loop is provided. The PFD compares phases and frequencies of an input signal and a feedback signal. The coarse tune low-pass filter module is coupled to the PFD and used for low-pass filtering a control signal with a gradually narrowed bandwidth to generate a filtered signal. The control signal indicates the comparison result of the input signal and the feedback signal. The VCO module has a first VCO gain and a second VCO gain, and generates an output signal according to the control signal and the filtered signal. The feedback loop provides the feedback signal to the PFD according to the output signal.