PLL Closed-Loop Bandwidth Measurement via VCO Tuning Oscillation
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Solution Overview
Problem
Current methods for measuring the closed-loop bandwidth of a Phase Locked Loop (PLL) are inadequate, as they often require precise voltage measurements, which are costly and energy-intensive, and do not accurately characterize the PLL under closed-loop conditions, leading to reduced modulation accuracy and limited modulation bandwidth.
Innovation Solution
A method that compares the VCO tuning voltage to low and high threshold voltages, generates an oscillation by offsetting the divider value, and measures the period of this oscillation using a reference clock signal to determine the relative loop bandwidth, allowing for more accurate and cost-effective characterization of the PLL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current voltage measurement techniques are used to measure PLL bandwidth, then measurement can be performed, but the measurement is costly and energy-intensive with reduced accuracy
Solution Approach 1:
The patent replaces voltage measurement (electrical domain) with frequency/period measurement (temporal domain). Instead of measuring the voltage value of the tuning signal directly, the method measures the period of oscillations in the tuning signal frequency, which can be done more accurately and efficiently using frequency counters or timer circuits.
Solution Approach 2:
The patent introduces an intermediary measurement approach by using the relationship between tuning voltage and VCO output frequency. The tuning voltage variations are converted into frequency variations that can be measured indirectly through the VCO output, providing a more accurate and energy-efficient measurement path.
2Productivity
If direct modulation of PLL is performed, then modulation can be implemented, but modulation accuracy is reduced due to low loop bandwidth
Solution Approach 1:
The patent applies pre-compensation to the modulation signal before it is applied to the PLL. By measuring the PLL's bandwidth characteristics and calculating the appropriate pre-distortion filter coefficients, the system pre-adjusts the modulation signal to compensate for the PLL's low-pass filtering effect, thereby maintaining modulation accuracy despite the limited loop bandwidth.
3Measurement precision
If pre-compensation is applied to compensate for low PLL bandwidth, then modulation accuracy can be improved, but the PLL bandwidth characteristics must be accurately known and monitored
Solution Approach 1:
The patent implements a self-measurement capability where the PLL system measures its own bandwidth characteristics using its own tuning signal. By injecting a test signal and measuring the resulting tuning signal oscillations, the system can autonomously determine its bandwidth without requiring external measurement equipment, simplifying the overall system architecture.
Data Source
AI summary
A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) (52) comprising a voltage controlled oscillator (VCO) (53) controlled by means of a tuning voltage (Vtune) is disclosed. An embodiment of the invention compares the VCO tuning voltage (Vtune) to a low threshold voltage (Vlow) and a high threshold voltage (Vhigh), creating an oscillation of the VCO tuning voltage by offsetting the divider value such that the PLL (52) forces the tuning voltage (Vtune) towards the high threshold voltage (Vhigh) when the low threshold voltage (Vlow) is reached, and offsetting the divider value such that said PLL (52) forces the tuning voltage (Vtune) towards the low threshold voltage (Vlow) when the high threshold voltage (Vhigh) is reached, measuring the period of the oscillation between the high and the low threshold voltage of the VCO tuning voltage by counting the number of cycles of a reference clock signal (clk), and comparing the number of reference clock cycles to a reference number of clock cycles to determine the relative loop bandwidth of the PLL (52).


