PLL Bandwidth Calibration Using Phase Disturbance Zero-Crossing
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Solution Overview
Problem
Existing PLL implementations face difficulties in meeting stricter specifications for high-speed communication standards due to process, voltage, and temperature variations, particularly in accurately measuring and adjusting bandwidth and peaking values to manage jitter effectively.
Innovation Solution
A calibration circuit is introduced to measure and fine-tune the bandwidth and peaking values of PLLs by inducing phase disturbances and measuring zero crossing times, allowing for precise estimation and adjustment of PLL parameters to meet challenging specifications, even in harsh environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If adjustment circuits are used to tune PLL parameters, then PLL output frequency can be adjusted, but the circuits fail to meet stricter PLL specifications under process, voltage, and temperature variations
Solution Approach 1:
The patent applies preliminary action by measuring the actual bandwidth and peaking values of the PLL before normal operation, and pre-calculating the necessary adjustment amounts. This allows the system to compensate for PVT variations in advance rather than reacting to them during operation, ensuring compliance with jitter specifications across all operating conditions.
Solution Approach 2:
The patent implements feedback by measuring the actual bandwidth and peaking values of the PLL and using these measurements to adjust the charge pump current. The system continuously monitors PLL performance parameters and feeds this information back to the adjustment circuit, enabling dynamic compensation for PVT variations and ensuring reliable compliance with specifications.
2Device complexity
If bandwidth and peaking values are not accurately measured and adjusted, then PLL can operate with simple circuits, but jitter propagation from reference clock to output clock exceeds specification limits
Solution Approach 1:
The patent replaces complex hardware adjustment mechanisms with a measurement and calculation-based approach. Instead of using complex mechanical or electrical tuning circuits, the system measures bandwidth and peaking values, calculates the necessary adjustments, and applies corrections through digital control of the charge pump current, thereby reducing overall circuit complexity while effectively controlling jitter propagation.
Solution Approach 2:
The patent changes the charge pump current parameter based on measured bandwidth and peaking values to optimize PLL performance. By dynamically adjusting this critical parameter, the system can control jitter propagation without requiring complex circuit architecture, achieving effective jitter management through parameter optimization rather than structural complexity.
3Manufacturing precision
If PLL bandwidth and peaking are tightly controlled to meet PCIE standards, then jitter propagation is reduced, but the adjustment circuits have difficulty meeting specifications under process, voltage, and temperature variations
Solution Approach 1:
The patent measures the actual bandwidth and peaking values before normal operation and pre-calculates the necessary adjustments to achieve target values. This preliminary measurement and adjustment approach ensures that the PLL is properly configured for the specific PVT conditions before operation begins, maintaining precision across varying conditions without requiring continuous complex adjustments.
Solution Approach 2:
The patent uses feedback by continuously monitoring the actual bandwidth and peaking values and adjusting the charge pump current accordingly. This closed-loop control mechanism ensures that the PLL maintains precise bandwidth and peaking control despite PVT variations, as the system automatically compensates for drift by feeding back performance measurements to the adjustment circuit.
Data Source
AI summary
A phase locked loop (PLL) system includes a PLL and a calibration circuit. The PLL has a reference clock input, a voltage controlled oscillator (VCO) clock output, and a feedback clock output. The calibration circuit provides a reference clock signal to the reference clock input of the PLL, induces first and second phase disturbances between the reference clock signal and a feedback clock signal, measures respective first and second zero crossing times of a phase error between the reference clock signal and the feedback clock signal, and estimates a bandwidth of the PLL in response to an average of the first and second zero crossing times.