Phase-Locked Loop Bandwidth Tuning With Stable Zero-Pole Ratios
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Solution Overview
Problem
Existing phase-locked loop circuits face challenges in balancing locking time and noise performance when adjusting loop bandwidth, leading to instability due to changes in the relationship between zero frequency, pole frequency, and loop bandwidth.
Innovation Solution
The phase-locked loop circuit includes an adjustable charge pump current, resistance, and capacitance values to maintain the ratios between zero frequency, pole frequency, and loop bandwidth unchanged, ensuring phase margin stability while allowing bandwidth adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the loop bandwidth is increased to reduce locking time, then the frequency locking speed is improved, but the noise performance deteriorates
Solution Approach 1:
The patent implements dynamic adjustment of loop bandwidth by configuring the loop filter with adjustable first and second capacitance values. The first capacitance value determines the loop bandwidth, while the second capacitance value determines the pole frequency. By dynamically switching between different capacitance values, the system can adapt the loop bandwidth to different operational requirements, achieving fast locking when needed while maintaining good noise performance when stable operation is required.
Solution Approach 2:
The patent changes the electrical parameters (capacitance values) of the loop filter to independently control different frequency characteristics. By adjusting the first capacitance value to change loop bandwidth and the second capacitance value to change pole frequency, the system can optimize performance for different operating conditions without compromising stability.
2Speed
If the loop bandwidth is changed to speed up frequency locking, then the locking time is reduced, but the phase margin stability deteriorates
Solution Approach 1:
The patent independently adjusts the first and second capacitance values to separately control loop bandwidth and pole frequency. This allows the system to change loop bandwidth for fast locking while simultaneously adjusting pole frequency to maintain optimal phase margin, thus achieving both speed and stability.
Solution Approach 2:
The patent creates an asymmetric control structure where the first capacitance value controls one parameter (loop bandwidth) and the second capacitance value controls another parameter (pole frequency). This asymmetric design allows independent optimization of different performance aspects, enabling fast locking without compromising phase margin stability.
3Productivity
If the loop bandwidth is increased to reduce locking time, then the frequency acquisition speed is improved, but the loop stability deteriorates due to changes in zero frequency and pole frequency relationships
Solution Approach 1:
The patent changes multiple parameters (first capacitance value for loop bandwidth, second capacitance value for pole frequency) in a coordinated manner. By adjusting these parameters together, the system can increase loop bandwidth for fast acquisition while maintaining the proper relationship between zero frequency and pole frequency to ensure loop stability.
Data Source
AI summary
The present disclosure relates to a phase-locked loop circuit and a signal processing device. The phase-locked loop circuit includes: a charge pump configured with a charge pump current; and a loop filter connected to the charge pump and configured with a first resistance value, a first capacitance value, and a second capacitance value, wherein a zero frequency of the phase-locked loop circuit is configured to be determined by the first resistance value and the first capacitance value, and a pole frequency of the phase-locked loop circuit is configured to be determined by the first resistance value and the second capacitance value; wherein at least two of the charge pump current, the first resistance value, the first capacitance value, and the second capacitance value are adjustable, to change a loop bandwidth of the phase-locked loop circuit, to maintain a first ratio between the zero frequency and the loop bandwidth unchanged, and to maintain a second ratio between the pole frequency and the loop bandwidth unchanged.