PLL Bias Control for Low-Voltage High-Speed Oscillation Stability
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Solution Overview
Problem
PLL circuits face challenges in operating at high speeds with low power source voltages while maintaining stability against temperature and process variations, leading to phase differences and oscillation frequency drifts.
Innovation Solution
A PLL circuit design that includes a phase comparator, an oscillation circuit, and a bias control circuit to increase the potential difference between the reference voltage and ground or power source voltage, allowing transistors to operate in a saturation area, thereby maintaining high-speed operation with low power source voltage and minimizing the impact of temperature and process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the control voltage Vcont is increased to obtain a high oscillation frequency of the VCO, then the oscillation frequency is improved, but the drain-source voltage Vds of the PMOS transistor decreases causing operation in the linear area and current variation
Solution Approach 1:
The invention changes the voltage parameter by introducing a boosted power source voltage VDD' that is higher than the normal power source voltage VDD. This voltage boosting allows the PMOS transistor to maintain adequate drain-source voltage even when control voltage increases, keeping the transistor in the saturation area and ensuring stable current operation at high oscillation frequencies
2Use of energy by moving object
If the power source voltage VDD is decreased to enable low power operation, then power consumption is reduced, but the drain-source voltage Vds of the PMOS transistor decreases causing operation in the linear area and current variation
Solution Approach 1:
The invention applies local quality by providing a specialized boosted power source voltage VDD' specifically for the charge pump circuit, while other circuits continue to operate at the normal low power source voltage VDD. This localized voltage boosting ensures the PMOS transistor in the charge pump maintains saturation operation and current stability without increasing overall system power consumption
3Productivity
If the PLL circuit operates at high speed with low power source voltage, then productivity is improved, but temperature and process variations cause phase differences and oscillation frequency drifts
Solution Approach 1:
The invention changes the voltage parameter by boosting the power source voltage to VDD' for the charge pump circuit, which stabilizes the current output against temperature and process variations. This ensures accurate phase comparison and frequency control, maintaining phase stability and preventing oscillation frequency drifts during high-speed operation
Data Source
AI summary
A PLL circuit includes a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal; an oscillation circuit, connected to the phase comparator, for outputting an oscillation signal having a frequency in accordance with the frequency control signal, a power source voltage, and a predetermined reference voltage; and a bias control circuit, connected to the oscillation circuit, for increasing either the potential difference between the reference voltage of the oscillation circuit and a ground voltage or the potential difference between the power source voltage of the oscillation circuit and the ground voltage. A transistor in the oscillation circuit can operate in a saturation area, thereby operating the PLL circuit at a high speed with a low power source voltage, without being easily affected by a variation in the temperature or other process conditions.