Fractional-N PLL Boundary-Timed Switching for Repeatable Phase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fractional-N phase-locked loops (PLLs) face challenges in maintaining phase coherence when switching between frequencies, leading to unpredictable phase relationships between output signals and reference clock signals, which affects performance in applications like radar and Bluetooth Low Energy (BLE) High Accuracy Distance Measurements.
Innovation Solution
The implementation of a fractional-N PLL with a multi-modulus divider and a pattern generator that supplies drive patterns to the divider at specific boundary times, resetting sigma-delta modulators to zero to ensure repeatable phase coherence across frequency changes, allowing for efficient switching without requiring all modulators to run continuously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fractional-N PLL switches between frequencies using conventional methods, then frequency change is achieved, but phase coherence is lost and phase relationships become unpredictable
Solution Approach 1:
The patent applies preliminary action by resetting the sigma-delta modulators to a known initial state (zero) before initiating frequency switching. This preliminary reset ensures that when the frequency transition occurs, the phase detector and feedback mechanism start from a deterministic point, guaranteeing predictable phase relationships in the output signal regardless of the frequency change path taken.
2Reliability
If all sigma-delta modulators run continuously to maintain phase coherence, then phase coherence is improved, but power consumption and silicon area increase
Solution Approach 1:
The patent implements periodic action by selectively activating only the necessary sigma-delta modulators based on the current frequency switching requirements. Instead of continuous operation, modulators are powered down when not needed and activated only during relevant frequency transitions, significantly reducing average power consumption while maintaining phase coherence through periodic reset and activation cycles.
Solution Approach 2:
The patent applies discarding and recovering by allowing sigma-delta modulators to be powered down (discarded from active operation) when their output is not currently needed for the target frequency. The modulators can be quickly reactivated (recovered) when frequency switching requires their functionality, optimizing the balance between maintaining phase coherence capabilities and minimizing power consumption during idle periods.
3Reliability
If all sigma-delta modulators run continuously to maintain phase coherence, then phase coherence is improved, but silicon area increases
Solution Approach 1:
The patent implements periodic action by selectively activating only the necessary sigma-delta modulators based on the current frequency switching requirements. Instead of continuous operation, modulators are powered down when not needed and activated only during relevant frequency transitions, significantly reducing average power consumption while maintaining phase coherence through periodic reset and activation cycles.
Solution Approach 2:
The patent applies universality by designing the sigma-delta modulator bank such that a single set of modulators can serve multiple frequency switching scenarios. By resetting modulators to a known state and activating only those needed for the current frequency transition, the same hardware resources are reused across different frequency operations, eliminating the need for dedicated modulators for each frequency and thus reducing total silicon area.
Data Source
AI summary
A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.