Compound PLL Clock Recovery With Frozen Frequency Between Bursts

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Solution Overview

Problem

Clock recovery in noisy bursty channels is challenging due to extraneous transitions caused by noise, making it difficult to maintain accurate timing during signal gaps and requiring a controlled oscillator with excellent precision, wide tuning range, and low phase noise, which existing technologies fail to achieve effectively.

Innovation Solution

A clock recovery circuit with an outer main tracking phase locked loop (PLL) and an analog/digital hybrid numerically controlled oscillator (NCO) that includes an inner PLL operating as a frequency synthesizer, where the phase detector is disabled during signal gaps and the NCO maintains the previous burst frequency, reducing phase creep and random walk, and using a burst detector to minimize channel noise influence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a local PLL is embedded within the clock recovery PLL to control a microwave oscillator, then the control system bandwidth can be widened to allow adequate response to signal bursts, but phase noise degradation occurs due to noise sources internal to the local PLL

Engineering Contradiction:
Improveresponse speedVSAvoidphase noise
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The system is divided into an outer clock recovery PLL and an inner local PLL frequency synthesizer. The outer loop handles coarse frequency acquisition and tracking with wide bandwidth, while the inner loop provides fine frequency control with narrow bandwidth to minimize phase noise. This segmentation allows each loop to be optimized for its specific function without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The NCO acts as an intermediary between the outer clock recovery PLL and the inner local PLL. It receives frequency control from the outer loop and provides precise frequency synthesis to the microwave oscillator through the inner loop, isolating the oscillator from direct control by the noisy outer loop while still enabling rapid response when needed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Stability of the object's composition

If the phase detector remains active during signal gaps to maintain tracking, then phase lock is maintained, but phase creep and random walk increase due to noise

Engineering Contradiction:
Improvephase lock stabilityVSAvoidphase creep and random walk
Core Design Contradiction:
Stability of the object's compositionVSObject-affected harmful factors

Solution Approach 1:

The phase detector operates periodically - active during signal bursts to acquire and track phase, and inactive during signal gaps to prevent noise-induced phase drift. The NCO maintains the last known good frequency value during gaps, and the inner local PLL keeps the oscillator running with minimal phase detector influence, achieving periodic tracking that balances stability with noise rejection.

Inventive Principle:
Principle #19Periodic action

3Object-affected harmful factors

If a microwave oscillator is used to provide low intrinsic noise, then phase noise is reduced, but frequency drift increases making accurate timing difficult

Engineering Contradiction:
Improvephase noiseVSAvoidfrequency stability
Core Design Contradiction:
Object-affected harmful factorsVSStability of the object's composition

Solution Approach 1:

The system merges the advantages of microwave oscillators (low phase noise) with digitally controlled frequency sources (low drift) by using the NCO to generate precise frequency control words that adjust the microwave oscillator's frequency. The oscillator provides the clean sinusoidal waveform while the digital controller provides accurate, drift-free frequency positioning through programmable division ratios.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10122527B1Signal phase tracking with high resolution, wide bandwidth and low phase noise using compound phase locked loop
Publication Date: 2018.11.06 NORTHROP GRUMMAN SYSTEMS CORP
  • US10122527B1 patent drawing
  • US10122527B1 patent drawing
  • US10122527B1 patent drawing

AI summary

A clock recovery circuit for providing clock recovery from a burst signal that is periodically present and absent in a noisy channel. The recovery circuit includes an outer main tracking second-order phase locked loop (PLL) having an analog phase detector, a digital loop filter, and an analog/digital hybrid numerically controlled oscillator (NCO) that operates so that the clock recovery frequency is “frozen” to its last value from the previous burst and the phase detector is disabled during the gaps between data bursts. The NCO is implemented with an inner loop PLL that operates as a high resolution synthesizer having a low internal control bandwidth that preserves VCO phase noise. The outer main loop achieves a higher control bandwidth through direct tuning of the inner loop VCO with the outer loop tuning signal.