PLL Calibration Lookup for Fast Phase Lock and Low Phase Noise

Solution Overview

Problem

Phase-locked loop circuits face challenges in reducing phase noise and achieving phase lock quickly due to high power consumption and long duration in achieving phase lock, primarily because of the need to compare numerous sub-bands to determine optimal sub-band settings.

Innovation Solution

The phase-locked loop circuit operates in calibration and phase-locked modes, determining voltage-controlled oscillator capacitor array control signals and charge pump current control signals for each frequency control word signal, allowing direct control of the voltage-controlled oscillator and charge pump to rapidly achieve phase lock, reducing the duration and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If the number of sub-bands of the VCO is increased to reduce gain KVCO and suppress phase noise, then phase noise is reduced, but the number of comparisons required increases, resulting in longer phase lock duration and higher power consumption

Engineering Contradiction:

Improvephase noiseVSAvoidphase lock duration

Core Design Contradiction:

Object-generated harmful factorsVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing the optimal sub-band selection for each frequency control word signal in a lookup table during the calibration mode. This pre-computation eliminates the need for time-consuming real-time comparisons during phase-locked mode, directly resolving the contradiction between reducing phase noise through multiple sub-bands and minimizing phase lock duration.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies preliminary action by pre-determining and storing the optimal charge pump current control signal for each frequency control word signal in the lookup table during calibration mode. This pre-computation allows the system to directly apply the optimal current setting during phase-locked mode without iterative adjustments, significantly reducing the time required to achieve phase lock while maintaining accuracy.

Inventive Principle:

Principle #10Preliminary action

2Object-generated harmful factors

If the number of sub-bands of the VCO is increased to reduce gain KVCO and suppress phase noise, then phase noise is reduced, but the number of comparisons required increases, resulting in higher power consumption

Engineering Contradiction:

Improvephase noiseVSAvoidpower consumption

Core Design Contradiction:

Object-generated harmful factorsVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing the optimal sub-band selection for each frequency control word signal in a lookup table during the calibration mode. This pre-computation eliminates the need for time-consuming real-time comparisons during phase-locked mode, directly resolving the contradiction between reducing phase noise through multiple sub-bands and minimizing phase lock duration.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces the mechanical comparison and iteration process with a digital lookup table mechanism. Instead of performing sequential comparisons of frequency errors across multiple sub-bands in real-time, the system uses a pre-computed lookup table that provides direct access to optimal settings, substituting a complex iterative mechanical process with a simple memory access operation that consumes significantly less power.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If traditional phase-locked loop operation is used with successive comparison of frequency errors, then optimal sub-band can be determined, but the number of comparisons is large, resulting in long phase lock duration

Engineering Contradiction:

Improveoptimal sub-band determinationVSAvoidphase lock duration

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing the optimal sub-band selection for each frequency control word signal in a lookup table during the calibration mode. This pre-computation eliminates the need for time-consuming real-time comparisons during phase-locked mode, directly resolving the contradiction between reducing phase noise through multiple sub-bands and minimizing phase lock duration.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11705913B2Phase-locked loop circuit and method for controlling the same

Publication Date: 2023.07.18 SILERGY SEMICON TECH (HANGZHOU) CO LTD

AI summary

A method for controlling a phase-locked loop circuit, can include: acquiring values of a voltage-controlled oscillator capacitor array control signal respectively corresponding to desired values of a frequency control word signal and acquiring values of a charge pump current control signal respectively corresponding to the desired values of the frequency control word signal in a calibration mode, where the frequency control word signal characterizes a ratio of a desired locked frequency to a frequency of a reference signal; and determining a target value of the voltage-controlled oscillator capacitor array control signal corresponding to a target value of the frequency control word signal and a target value of the charge pump current control signal corresponding to the target value of the frequency control word signal in a phase-locked mode, in order to control the phase-locked loop circuit to achieve phase lock.