On-Chip PLL Calibration Using NVM to Offset Process Variations
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Solution Overview
Problem
Conventional integrated circuit (IC) devices face challenges in accurately defining design parameters due to uncontrollable variations in active and passive components during fabrication, leading to the need for costly and complex post-fabrication trimming and over-designing to accommodate component variations, which increases manufacturing complexity and costs.
Innovation Solution
The integration of processor circuits within the IC device to perform calibration routines using stored calibration values in nonvolatile memory, allowing for on-the-fly calibration of phase or delay lock loop circuits, charge pump currents, resistor-capacitor networks, and loop gain, thereby compensating for manufacturing and operating variations without additional post-fabrication steps or over-designing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional post-fabrication trimming is used to compensate for component variations, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies preliminary action by performing calibration during the fabrication process itself rather than after fabrication. The calibration circuit measures and adjusts component parameters in-situ before the device is completed, eliminating the need for separate post-fabrication trimming steps and reducing overall manufacturing complexity.
Solution Approach 2:
The patent replaces mechanical post-fabrication trimming operations with an electronic calibration system. Instead of physically adjusting components after fabrication, an on-chip calibration circuit electronically measures and compensates for variations, substituting mechanical adjustment with electronic correction.
2Reliability
If over-designing is used to accommodate component variations, then reliability is improved, but device size and cost increase
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting circuit parameters through calibration rather than designing for worst-case variations. The calibration circuit measures actual component parameters and adjusts operating points accordingly, allowing the device to achieve reliable performance with smaller, optimized component values instead of oversized conservative designs.
Solution Approach 2:
The patent implements self-service through an on-chip calibration circuit that automatically measures and compensates for component variations without external intervention. The device calibrates itself during fabrication, eliminating the need for external trimming equipment and complex post-fabrication processes, thereby reducing device area and cost while maintaining reliability.
3Manufacturing precision
If conventional trimming processes are used, then manufacturing precision is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent performs calibration as a preliminary action during the fabrication process itself, measuring and adjusting component parameters before the device is completed. This eliminates the need for separate post-fabrication trimming and testing steps, significantly reducing manufacturing time while maintaining high precision.
Solution Approach 2:
The patent merges the calibration function with the fabrication process by integrating the calibration circuit directly on the chip. Instead of separating fabrication and calibration into distinct stages, the calibration circuit is fabricated alongside the main device and performs adjustments in-situ, combining multiple processes into one efficient workflow.
Data Source
AI summary
An integrated circuit (IC) device can include at least one phase or delay lock loop (P/DLL) circuit comprising a plurality of circuit sections, at least one of the circuit sections responsive to digital calibration values to alter at least one periodic output signal; a nonvolatile memory (NVM) circuit formed in the same IC package as the at least one P/DLL circuit and configured to store the calibration values; and a processing circuit formed in the same IC package as the at least one P/DLL circuit and the NVM circuit, the processing circuit configured to generate the calibration values in response to target values and output values from the at least one P/DLL circuit, and to store the calibration values in the NVM circuit.