Phase-Locked Loop Calibration for Repetitive Phase Error Correction
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Solution Overview
Problem
Conventional phase-locked loops in self-servo-write processes of hard disk drives face challenges with repeatable and non-repeatable phase errors due to spindle speed variations and written-in rotational timing mark errors, leading to non-uniform placement of servo sectors, which can be mitigated but at the cost of increased system noise and reduced stability.
Innovation Solution
A method and apparatus that include an oscillator model, averaging and summing submodules, and a delay buffer to generate and refine repetitive phase error corrections, which are used to calibrate phase-locked loops, reducing phase errors and improving servo sector placement accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the bandwidth of the PLL is increased to minimize phase errors, then the accuracy of servo sector placement is improved, but system noise increases and stability is reduced
Solution Approach 1:
The patent segments the phase error into two distinct components: repetitive phase errors (which occur periodically with each spindle rotation) and non-repetitive phase errors (which are random or aperiodic). By separating these error types, the system can apply different correction strategies to each, allowing for improved phase accuracy without compromising stability. The repetitive error correction module specifically targets the periodic component, enabling precise correction without requiring excessive bandwidth that would amplify noise.
Solution Approach 2:
The patent implements preliminary action by predicting and correcting repetitive phase errors before they affect servo sector placement. The repetitive error correction module anticipates periodic phase deviations based on previous rotations and applies corrective adjustments in advance. This proactive approach allows the system to maintain high accuracy without needing to increase PLL bandwidth, thereby preserving system stability.
2Measurement precision
If the bandwidth of the PLL is increased to minimize phase errors, then the precision of servo sector placement is improved, but system noise increases
Solution Approach 1:
By segmenting phase errors into repetitive and non-repetitive components, the system can selectively correct only the repetitive portion using the dedicated correction module. This targeted approach improves servo sector placement precision without requiring a high-bandwidth PLL, thereby avoiding the amplification of system noise that would result from increasing bandwidth.
Solution Approach 2:
The patent extracts the repetitive phase error component from the total phase error signal and processes it separately through the repetitive error correction module. By isolating and correcting only the periodic component, the system achieves improved precision without needing to increase overall PLL bandwidth, thus preventing noise amplification.
3Speed
If conventional PLL control is used to synchronize SSW clock to rotational timing marks, then basic synchronization is achieved, but repeatable and non-repeatable phase errors result in non-uniform placement of servo sectors
Solution Approach 1:
The patent implements feedback by continuously monitoring phase errors between the SSW clock and rotational timing marks, and using this information to adjust the clock synchronization. The repetitive error correction module specifically feeds back corrected phase error values to compensate for periodic deviations, enabling uniform servo sector placement while maintaining basic synchronization.
Solution Approach 2:
The repetitive error correction module acts as an intermediary between the basic PLL synchronization and the final servo sector placement. It receives the phase error signal from the PLL, processes it to remove repetitive components, and outputs a corrected signal that improves placement uniformity without disrupting the fundamental clock synchronization function.
Data Source
AI summary
Methods, systems, and apparatus, including computer program products, are described for calibrating control loops, specifically phase-locked loops. In one aspect, an apparatus is provided that includes an oscillator model that generates a predicted phase based on an input, a first averaging submodule that generates an average predicted phase over a predetermined number of samples, and a first summing submodule that receives a first corrected phase error and generates a predicted repetitive phase disturbance using the first corrected phase error, the predicted phase, and the average predicted phase.