Digital Fractional-N PLL Calibration for TDC Linearity Errors
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Solution Overview
Problem
Current digital fractional frequency-division phase-locked loops face challenges in improving the linearity of time-to-digital converters (TDCs) due to component mismatch and layout design issues, leading to high power consumption, area requirements, and complexity, making it difficult to maintain low noise levels.
Innovation Solution
A digital frequency-division phase-locked loop with a non-linear calibration method that uses a calibration apparatus to compensate for phase differences between reference and feedback clock signals, employing a sigma-delta modulator to generate frequency control words and perform digital filtering, allowing for non-linear calibration without enhancing the TDC, thus reducing implementation expenses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the linearity of the TDC is improved by addressing component mismatch and layout design mismatch, then the noise level of the phase-locked loop system is reduced, but the power consumption, area, and complexity increase significantly
Solution Approach 1:
The patent introduces a calibration apparatus as an intermediary component that measures and compensates for the non-linear error of the TDC. Instead of modifying the TDC structure itself, the calibration apparatus acts as a mediator that characterizes the TDC's non-linearity and applies corrective calibration data, thereby improving measurement precision without increasing TDC complexity
Solution Approach 2:
The patent changes the operational parameters of the system by introducing calibration data that characterizes the TDC's non-linear behavior at different operating points. By measuring and storing calibration parameters (non-linear error values) at various frequency control words and division ratios, the system compensates for TDC non-linearity through parameter adjustment rather than structural modification
2Measurement precision
If the linearity of the TDC is improved by addressing component mismatch and layout design mismatch, then the noise level of the phase-locked loop system is reduced, but the power consumption increases
Solution Approach 1:
The calibration apparatus serves as an intermediary that measures and compensates for TDC non-linearity without requiring modifications to the TDC's power-consuming structure. The calibration process and compensation mechanism are implemented separately, allowing noise reduction through improved linearity measurement while avoiding the power penalty that would result from redesigning the TDC itself
3Measurement precision
If the linearity of the TDC is improved by addressing component mismatch and layout design mismatch, then the noise level of the phase-locked loop system is reduced, but the area requirements increase
Solution Approach 1:
The calibration apparatus is implemented as a separate intermediary system that does not require modification of the TDC's physical structure. By measuring and compensating for non-linearity through calibration data rather than structural changes, the patent achieves improved measurement precision without increasing the area occupied by the TDC itself
Solution Approach 2:
The patent creates a digital copy or model of the TDC's non-linear behavior through calibration measurements. Instead of physically modifying the TDC structure to improve linearity, the system creates a calibration data set that replicates and compensates for the non-linear characteristics, thereby achieving improved precision without additional hardware area
Data Source
AI summary
A digital frequency-division phase-locked loop, including a time-to-digital converter (TDC), a digital loop filter (DLF), a digital-controlled oscillator (DCO), a feedback frequency divider (DIV), a sigma-delta modulator (SDM), and a calibration apparatus, where the calibration apparatus compensates for, based on a frequency control word and a frequency-division control word generated by the SDM, a digital signal output by the TDC to obtain a calibration signal. The DLF performs digital filtering on the calibration signal to obtain an oscillator frequency control signal and set the oscillator frequency control signal as an output signal of the DCO.