Charge Pump PLL Capacitance Multiplication for Stable Small-Area Loops
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Solution Overview
Problem
Designing charge pump phase-locked loop (PLL) circuits faces challenges in stability, where increased capacitance is required for stability, leading to larger circuit areas and higher costs.
Innovation Solution
The implementation of a decimator in the charge pump PLL circuit allows for capacitance multiplication by decimating phase error information, effectively increasing the apparent capacitance without the need for large physical capacitors, thereby achieving stability with reduced area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitance of the integral charge pump path is increased to improve stability, then the stability of the charge pump PLL is improved, but the circuit area and cost increase
Solution Approach 1:
The patent changes the operating parameters of the charge pump by introducing a decimator that operates at a reduced frequency (divided by N). This parameter change allows the system to achieve the same stability effect with a smaller capacitor, as the decimated phase error information requires less charge storage capacity to maintain loop stability.
Solution Approach 2:
The decimator acts as an intermediary component between the phase detector and the integral charge pump. It processes the phase error information and generates decimated error signals that are then fed to the integral charge pump, enabling the system to achieve stability with reduced capacitance requirements.
2Reliability
If the capacitance of the integral charge pump path is increased to improve stability, then the stability of the charge pump PLL is improved, but the cost increases
Solution Approach 1:
By changing the frequency parameter through decimation, the patent reduces the required capacitance value, which directly lowers component cost and manufacturing complexity while maintaining the necessary stability performance.
3Reliability
If a decimator is introduced to multiply capacitance effect, then the apparent capacitance increases with smaller physical capacitors, but the device complexity increases
Solution Approach 1:
The patent segments the charge pump functionality into two distinct paths: a proportional charge pump operating at the original frequency and an integral charge pump operating at the decimated frequency. This segmentation allows each path to perform its specific function with optimized components, achieving stability without requiring a single large capacitor.
Solution Approach 2:
The decimator serves as an intermediary that enables the integral charge pump to operate at a lower effective frequency, creating the capacitance multiplication effect while adding only moderate complexity through a frequency division mechanism.
Data Source
AI summary
A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages.