FMCW PLL Variable Capacitance for Reset Time and Phase Noise
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Solution Overview
Problem
FMCW PLL implementations in radar systems face challenges in efficiently managing phase noise and reset time due to fixed bandwidth settings, which affect dynamic range and power consumption.
Innovation Solution
Dynamic adjustment of PLL bandwidth using variable capacitance in low-pass filter circuitry, combined with current injection by a DAC and charge pump circuitry, allows for different bandwidth settings during acquisition and reset periods, mitigating phase noise and reducing reset time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a higher PLL bandwidth is used during reset period to reduce reset time, then reset time is reduced, but phase noise increases during acquisition period
Solution Approach 1:
The patent implements dynamic adjustment of PLL bandwidth by switching capacitor banks in the low-pass filter circuitry. The capacitance value changes based on operational phase: lower capacitance (higher bandwidth) during reset period for fast settling, and higher capacitance (lower bandwidth) during acquisition period for reduced phase noise. This dynamic reconfiguration resolves the contradiction by adapting the bandwidth to the specific operational requirements of each phase.
Solution Approach 2:
The patent changes the electrical parameter (capacitance) of the low-pass filter to control PLL bandwidth. By switching between different capacitor bank configurations, the system transitions between different bandwidth states: narrow bandwidth during acquisition to minimize phase noise, and wide bandwidth during reset to accelerate settling. This parameter change strategy directly addresses the trade-off between reset time and phase noise.
2Object-affected harmful factors
If a narrow PLL bandwidth is used during acquisition period to reduce phase noise, then phase noise is reduced, but reset time increases
Solution Approach 1:
The system dynamically switches the low-pass filter capacitance based on the operational phase. During acquisition, the capacitor banks are configured to provide higher capacitance for narrow bandwidth and low phase noise. During reset, the capacitor banks are reconfigured to provide lower capacitance for wide bandwidth and fast settling. This dynamic adaptation resolves the contradiction by optimizing bandwidth for each specific phase requirement.
Solution Approach 2:
The patent utilizes parameter changes in the low-pass filter capacitance to control the PLL bandwidth characteristics. The capacitance value is adjusted between two distinct states: a higher value during acquisition for noise reduction, and a lower value during reset for speed optimization. This parameter switching mechanism effectively resolves the trade-off between phase noise performance and reset speed.
3Device complexity
If fixed bandwidth settings are used in PLL circuitry, then circuit complexity is reduced, but dynamic range and power consumption are adversely affected
Solution Approach 1:
The low-pass filter capacitance is segmented into multiple switchable capacitor banks. Each bank can be independently switched in or out of the circuit based on operational phase. This segmentation allows the system to achieve variable bandwidth characteristics without requiring a completely different circuit architecture for each mode, thus maintaining relatively simple circuitry while enabling dynamic performance optimization for both acquisition and reset phases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces phase noise during acquisition and minimizes reset time, enhancing the dynamic range and reducing power consumption in radar systems by optimizing bandwidth settings dynamically.
Implementation Method 1
variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for at least one slope
Implementation Method 2
a charge pump (CP) circuitry... the CP may inject current, at reset time, into one or more capacitors associated with the LPF
Implementation Method 3
a digital and analog converter (DAC) for current injection to the LPF capacitors for pre-charging filter capacitance
Data Source
AI summary
Exemplary aspects of the present disclosure involve a system and related method of PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth (BW). To adjust the BW, the PLL circuitry may provide for variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for one slope, as used for the acquisition period. The capacitance may then be adjusted to allow for a different bandwidth for another slope which is used to reset the circuitry in preparation for another frequency sweep. Adjusting the PLL BW, via variable capacitance, may be used to mitigate phase noise which can adversely the PLL.