Phase-Locked Loop Circuit Capacitor Cell Control for Low Frequency Locking
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Solution Overview
Problem
Phase-locked loop (PLL) circuits face increased time requirements to output a phase-locked signal in low frequency bands due to the need for more precise control of capacitor cells.
Innovation Solution
A phase-locked loop circuit with a control logic circuit that compares a target frequency with an oscillator's output frequency, generates input and output codes to control capacitor cells, and adjusts the electrical path to reduce the time required for the oscillator to output a signal with the desired frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If precise control of capacitor cells is implemented to support low frequency bands, then frequency control precision is improved, but the time required to output a phase-locked signal increases
Solution Approach 1:
The capacitor cell array is divided into multiple groups (first group, second group, third group) that can be independently controlled. This segmentation allows the control logic circuit to selectively activate only the necessary capacitor cells for the target frequency, rather than precisely controlling all capacitor cells, thereby reducing the time required to achieve frequency locking while maintaining control precision.
Solution Approach 2:
The control logic circuit预先 determines which capacitor cells need to be controlled based on the target frequency before actual frequency adjustment begins. By pre-planning the control strategy and pre-configuring the electrical path selection, the system minimizes the time required to output the phase-locked signal while maintaining precise frequency control.
2Productivity
If multiple capacitor cells are controlled to reduce output time, then productivity is improved, but device complexity increases
Solution Approach 1:
The capacitor cell array is divided into multiple groups (first group, second group, third group) that can be independently controlled. This segmentation allows the control logic circuit to selectively activate only the necessary capacitor cells for the target frequency, rather than precisely controlling all capacitor cells, thereby reducing the time required to achieve frequency locking while maintaining control precision.
Solution Approach 2:
The control logic circuit dynamically selects which capacitor cells to control based on the target frequency requirements. For low frequency bands, it controls multiple capacitor cells simultaneously, while for high frequency bands, it controls fewer cells. This dynamic adaptation optimizes the balance between locking speed and control complexity for different operating conditions.
Data Source
AI summary
A phase-locked loop circuit includes an oscillator including a plurality of capacitor cells, and a control logic circuit that receives an output from the oscillator. The control logic circuit compares a target frequency with a first frequency of a first signal output from the oscillator, generates a first input code to control at least a portion of the plurality of capacitor cells to output a signal having the target frequency based on the comparison, generates a first output code corresponding to the first input code when the first input code is within a predetermined range of input codes, and controls at least two capacitor cells from among the plurality of capacitor cells based on the first output code. The oscillator may output a second signal having a second frequency through an electrical path including capacitor cells other than grounded capacitor cells from among the plurality of capacitor cells.