Capacitor Multiplier for Phase-Locked Loop Area Reduction
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Solution Overview
Problem
Phase-locked loop (PLL) circuits face limitations in reducing capacitor size and area on integrated circuits while maintaining effective capacitance, which affects their performance in frequency adjustment and noise suppression.
Innovation Solution
Incorporating a capacitor multiplier that divides the current generated by a charge pump, allowing for reduced capacitor size by amplifying effective capacitance, thereby shrinking the physical area required for capacitors in PLL circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If capacitor size is reduced to shrink chip area, then area occupation is reduced, but effective capacitance decreases affecting frequency adjustment and noise suppression performance
Solution Approach 1:
A capacitor multiplier circuit is introduced as an intermediary component between the charge pump and the capacitor. This circuit multiplies the charging current (e.g., 4x multiplication), allowing a smaller capacitor (500pF) to achieve the same effective capacitance as a larger capacitor (2nF) would provide in conventional designs, thus resolving the contradiction between reduced area and maintained performance
Solution Approach 2:
The invention changes the current parameter by introducing a capacitor multiplier that increases the charging current to the capacitor. By multiplying the current from the charge pump (e.g., converting I to 4I), the effective capacitance is enhanced without increasing the physical capacitor size, allowing area reduction while maintaining frequency adjustment and noise suppression capabilities
2Area of stationary object
If capacitor size is reduced to shrink chip area, then area occupation is reduced, but noise suppression capability deteriorates
Solution Approach 1:
The capacitor multiplier circuit serves as an intermediary that enhances the charging current to the capacitor. This current multiplication (e.g., 4x) compensates for the reduced capacitor size, maintaining the noise suppression capability that would otherwise be lost with a smaller capacitor, thus resolving the contradiction between area reduction and noise suppression
Solution Approach 2:
By changing the current parameter through the capacitor multiplier (transforming current I into multiplied current nI), the invention maintains the effective capacitance value needed for noise suppression while using a physically smaller capacitor, thereby reducing chip area without compromising noise filtering performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a significant reduction in capacitor size from 2 nF to 500 pF, allowing for more compact chip designs while maintaining or improving the PLL's frequency adjustment and noise suppression capabilities.
Implementation Method 1
The charge pump, which includes a positive output node and a negative output node, receives the up/down signal to generate a current signal
Implementation Method 2
The capacitor is coupled to the negative output node
Implementation Method 3
The capacitor multiplier, coupled to the negative output node, generates a second current signal which is the current signal divided by a scaling number
Data Source
AI summary
A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.