PLL Carrier Tracking With Feedback Pause for Unstable NFC Clocks
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Solution Overview
Problem
In near-field communication (NFC) card emulation mode, phase-lock loop (PLL) circuits in mobile devices face challenges in tracking a reliable radiofrequency (RF) carrier due to amplitude modulation and active load modulation, leading to phase and frequency errors when the clock reference becomes unreliable.
Innovation Solution
A time-limited gating mechanism and feedback-pause-control are implemented in the PLL circuit to limit phase and frequency errors during unreliable clock references, using a time limiter circuit with absolute phase detection, delay timer, and pulse gating to adjust phase tracking signals, and a feedback-pause-controller to ensure correct initial compensation decisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the PLL continuously tracks the RF carrier to maintain accurate clock recovery, then clock accuracy is improved, but phase and frequency errors increase when the clock reference becomes unreliable due to amplitude modulation and active load modulation
Solution Approach 1:
The system dynamically switches between tracking mode and pause mode based on the reliability of the clock reference. The phase detector operates differently in each mode: in tracking mode it normaly adjusts phase and frequency, while in pause mode it limits adjustments to prevent error accumulation. This dynamic adaptation resolves the contradiction by allowing accurate tracking when the reference is reliable while preventing error propagation when the reference becomes unreliable due to amplitude modulation and active load modulation.
Solution Approach 2:
The invention changes the operational parameters of the phase detector based on reference reliability. When the clock reference is determined to be unreliable, the system modifies the phase detector's behavior to limit phase and frequency adjustments rather than continuously correcting. This parameter change allows the system to maintain stability during unreliable periods while achieving accurate clock recovery during reliable periods.
2Reliability
If the PLL stops tracking the RF carrier when the clock reference is unreliable, then phase and frequency error accumulation is reduced, but reacquisition time increases when the reference becomes reliable again
Solution Approach 1:
The system prepares for rapid reacquisition by maintaining the phase detector in a ready state during pause mode, rather than completely disabling it. The feedback-pause-control mechanism ensures that when the clock reference becomes reliable again, the phase detector can immediately resume normal tracking operations without requiring a lengthy reinitialization period. This preliminary preparation minimizes reacquisition time while still preventing error accumulation during unreliable periods.
3Speed
If the phase detector makes rapid initial compensation decisions upon returning to tracking mode, then reacquisition speed is improved, but incorrect compensation decisions increase causing phase and frequency errors
Solution Approach 1:
The feedback-pause-control mechanism uses feedback about the reliability status of the clock reference to control the phase detector's operation. When the reference is determined to be reliable, the system provides feedback that enables the phase detector to resume tracking. The controlled resumption ensures that initial compensation decisions are made with proper reference validation, preventing incorrect adjustments while maintaining rapid reacquisition. The feedback loop validates the reference quality before allowing aggressive compensation actions.
Data Source
AI summary
Techniques are described for accurate tracking of a radiofrequency (RF) carrier for amplitude-modulated signals in unstable reference clock environments. For example, some embodiments operate in context of clock circuits in devices configured for near-field communication (NFC) card emulation (CE) mode. The clock circuits seek to generate an internal clocking signal by tracking a clock reference, such as an RF carrier. In some cases, the clock reference can unpredictably become unreliable for periods of time, during which continued tracking of the unreliable clock reference and/or improper reacquisition can yield appreciable frequency and phase errors in the generated internal clocking signal. Some embodiments implement phase delta detection with time limiting to limit the magnitude of such errors in the internal clocking signal introduced while tracking an unreliable clock reference. Other embodiments provide feedback-pause-control (FPC) to force proper clock reference reacquisition. Such FPC can be implemented additionally with time-limited phase detection.