Phase-Locked Loop Charge Compensation for Faster Radar Modulation
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Solution Overview
Problem
Radar sensors face a trade-off between achieving fast modulation for improved velocity resolution and minimizing phase noise, as increasing bandwidth for fast modulation compromises phase noise reduction, and existing solutions fail to effectively shorten the duration of frequency modulated signals within the constraints of radar chip size and stable circuit operations.
Innovation Solution
A phase-locked loop system incorporating a digital modulation controller and charge compensation circuit to generate frequency modulated signals with reduced invalid intervals, allowing for faster modulation and improved measurement accuracy by regulating charges during invalid intervals and quickly relocking the phase-locked loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bandwidth of the phase-locked loop is increased to achieve fast modulation, then the modulation speed is improved, but the phase noise increases
Solution Approach 1:
The patent segments the frequency modulated signal into valid intervals and invalid intervals. The phase-locked loop operates in a locked state during valid intervals for accurate modulation, and transitions to an unlocked state during invalid intervals to reduce phase noise accumulation. This temporal segmentation allows the system to achieve fast modulation when needed while minimizing phase noise during transition periods.
Solution Approach 2:
The patent implements periodic switching between locked and unlocked states of the phase-locked loop. By periodically controlling the valid and invalid intervals of the frequency modulated signal, the system achieves fast modulation through the locked state while reducing phase noise through the unlocked state, thereby resolving the contradiction between modulation speed and phase noise.
2Measurement precision
If the period of the frequency modulated signal is shortened to improve detection resolution, then the detection resolution is improved, but the circuit transformations increase
Solution Approach 1:
The patent dynamically controls the duration of valid and invalid intervals of the frequency modulated signal to optimize detection resolution. By adjusting the time-domain characteristics of the signal without requiring complex circuit transformations, the system achieves shorter periods for improved detection resolution while maintaining circuit stability.
Solution Approach 2:
The patent changes the temporal parameters (valid interval duration, invalid interval duration) of the frequency modulated signal to achieve shorter periods for improved detection resolution. This parameter adjustment approach avoids complex circuit transformations and maintains stability of existing circuits.
3Productivity
If more frequency modulated signals are transmitted for the same length of time, then the detection resolution is improved, but the frequency callback duration increases
Solution Approach 1:
The patent extracts and eliminates the frequency callback portion from the frequency modulated signal by designating it as an invalid interval. By removing the frequency callback duration and replacing it with a valid interval that directly contributes to detection, the system increases the signal transmission rate without proportionally increasing the total time required.
Solution Approach 2:
The patent skips the traditional frequency callback portion of the phase-locked loop cycle by implementing an invalid interval that does not require full relocking. This allows the system to rapidly transition between signal transmission cycles, thereby increasing the number of frequency modulated signals that can be transmitted within the same time period.
Data Source
AI summary
The present disclosure provides a phase-locked loop, a radio frequency transmitter, a radar sensor and an electronic device. The phase-locked loop includes a phase-locked loop circuit, a charge compensation circuit and a digital modulation controller. The phase-locked loop circuit is connected to the charge compensation circuit. The digital modulation controller is connected to the phase-locked loop circuit and configured to output a frequency control signal so as to cause the phase-locked loop circuit to generate a valid interval of a frequency modulated signal in accordance with the frequency control signal. The digital modulation controller is further connected to the charge compensation circuit and configured to control the charge compensation circuit to regulate charges in the phase-locked loop circuit during an invalid interval of the frequency modulated signal to shorten a duration of frequency callback of the frequency modulated signal.