PLL Charge Pump Current Mirror Layout for Noise and Area Reduction
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Solution Overview
Problem
Existing charge pump circuits in phase-locked loop (PLL) systems face challenges in minimizing noise and reducing the size of the circuit while maintaining signal quality, as increasing transistor sizes to reduce noise leads to increased installation area and complex design steps.
Innovation Solution
The charge pump circuit configuration includes independently sized current mirrors, where only the transistors contributing to noise are increased in size, and noise is canceled in the charge and discharge cycles, allowing for reduced transistor sizes and simplified design without amplifiers or extra switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If transistor sizes are increased to reduce noise, then noise is reduced, but installation area increases
Solution Approach 1:
The charge pump circuit is divided into separate current mirrors (first, second, third current mirrors) with independent transistor sizing. Only the transistors that contribute to noise (those in the signal path during charge and discharge cycles) are increased in size, while other transistors maintain standard sizes. This segmentation allows selective noise reduction without proportionally increasing the entire circuit area.
Solution Approach 2:
Different transistor sizes are assigned to different parts of the circuit based on their functional requirements. The transistors in the current mirrors that directly affect noise performance are made larger, while transistors in non-critical paths maintain smaller sizes. This local differentiation optimizes noise reduction while minimizing area consumption.
2Object-affected harmful factors
If transistor sizes are increased to reduce noise, then noise is reduced, but design complexity increases
Solution Approach 1:
The circuit is segmented into modular current mirror blocks with standardized interfaces. Each current mirror can be designed and analyzed independently, simplifying the overall design process. The segmentation allows designers to focus on optimizing specific noise-critical sections without having to redesign the entire circuit.
Solution Approach 2:
The patent uses replicated current mirror structures (first, second, third current mirrors) with similar topologies. Once a current mirror design is optimized, it can be copied and adapted for different functions, reducing design complexity and ensuring consistency across the circuit.
3Object-affected harmful factors
If circuit components are added to reduce noise, then noise is reduced, but device complexity increases
Solution Approach 1:
The charge pump circuit uses the existing current mirrors and switching mechanisms to achieve noise reduction without requiring additional dedicated noise-filtering components. The circuit leverages its own operational cycles (charge and discharge) to naturally cancel noise through the coordinated operation of the current mirrors, eliminating the need for extra amplifiers or filters.
Solution Approach 2:
The current mirrors serve multiple functions: they generate the charge and discharge currents, provide noise reduction through their sizing, and enable the phase-locked loop operation. This multi-functionality eliminates the need for separate noise-reduction circuits, maintaining simplicity while achieving noise suppression.
Data Source
AI summary
According to one embodiment, a charge pump circuit includes: a current source; a first current mirror including an input terminal connected to the current source; a second current mirror including an input terminal connected to an output terminal of the first current mirror; a third current mirror including an input terminal connected to a first output terminal of the second current mirror; a first switch including a first end connected to a second output terminal of the second current mirror via a first node, and including a second end; and an output terminal connected to an output terminal of the third current mirror and the second end of the first switch via a second node.