PLL Charge Pump Circuit for Low-Current Noise and Phase Error
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Solution Overview
Problem
Phase-locked loops (PLLs) face imperfections in charge pumping due to mismatched charge coupling and channel charge dispersion, leading to worsened static phase error, deterministic jitter, and reference spur pass-through, particularly when handling smaller currents, which affects signal-to-noise ratio (SNR) and PLL performance.
Innovation Solution
The charge pump design includes a p-channel source current network and n-channel sink current network configured to draw and channel baseline currents, with p-channel and n-channel current switches that split currents in specific ratios, and a voltage buffer to maintain output voltage, enabling improved SNR by handling smaller currents while maintaining PLL loop dynamics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional charge pump circuits are used, then basic PLL functionality is achieved, but static phase error, deterministic jitter, and reference spur pass-through worsen due to mismatched charge coupling and channel charge dispersion
Solution Approach 1:
The charge pump circuit is segmented into separate p-channel source current network and n-channel sink current network, each with dedicated transistors and current switches. This segmentation allows independent optimization of charge coupling paths, reducing mismatch between source and sink operations and improving PLL performance while reducing static phase error.
Solution Approach 2:
Different transistor types (p-channel and n-channel) are used in specific regions of the circuit to optimize local charge coupling characteristics. The p-channel transistors are configured for sourcing current while n-channel transistors handle sinking, with each region optimized for its specific function to minimize charge dispersion and improve measurement precision.
2Quantity of substance
If conventional charge pump circuits are used, then basic current switching is achieved, but signal-to-noise ratio deteriorates when handling smaller currents
Solution Approach 1:
The circuit parameters such as transistor sizing, current levels, and switching timings are optimized to maintain adequate signal-to-noise ratio when handling smaller currents. By carefully adjusting these parameters in the segmented charge pump architecture, the circuit achieves better noise performance while operating at reduced current levels.
3Device complexity
If simpler charge pump circuits are used, then device complexity is reduced, but charge coupling mismatch and channel charge dispersion increase
Solution Approach 1:
The charge pump is divided into distinct p-channel and n-channel networks with dedicated transistors and current paths. This segmentation, while increasing device complexity, enables precise matching of charge coupling characteristics in each network, thereby improving manufacturing precision and reducing charge dispersion.
Solution Approach 2:
Dedicated current switches and transistor networks act as intermediaries between the phase comparator and the output, providing controlled charge transfer paths. These intermediary elements enable precise charge coupling while isolating the main circuit from direct charge dispersion effects.
Data Source
AI summary
A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.