PLL Charge Pump Compensation for Missing Clock Pulse Phase Bumps
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Solution Overview
Problem
Conventional phase locked loops (PLLs) experience phase bumps due to missing pulses in the reference clock, leading to phase errors and instability, as existing solutions either fail to promptly correct the phase or do not provide adequate compensating pulses to counteract the errors caused by missing pulses.
Innovation Solution
A control circuitry in the PLL detects missing pulses and generates pulse-width limited signals to manage the charge pump, ensuring immediate correction of phase errors by generating compensating UP pulses after DN pulses, with specific current adjustments during different charging periods to minimize phase deviation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the phase-frequency detector output is not reset after a missing pulse, then the phase error detection continues, but the phase bump increases and stability is lost
Solution Approach 1:
The patent applies preliminary action by resetting the phase-frequency detector output and generating compensating pulses before the phase error can cause significant phase bump. The control circuitry detects the missing pulse condition and immediately initiates correction by generating compensating UP pulses that counteract the stuck DN pulse, preventing rather than merely responding to phase instability.
2Reliability
If a compensating pulse is generated after several clock cycles, then the phase error is eventually corrected, but the phase bump persists during the delay period
Solution Approach 1:
The patent implements skipping by rushing through the phase correction process immediately upon detecting a missing pulse. Instead of waiting for several clock cycles, the control circuitry generates compensating pulses in the next immediate clock cycle, skipping the delay period that would otherwise allow phase bump to accumulate. This urgent correction approach minimizes the time loss while maintaining reliable phase error compensation.
3Object-generated harmful factors
If the DN pulse is pulse-width limited, then the charge removal is restricted, but the phase error compensation is insufficient without a corresponding UP pulse
Solution Approach 1:
The patent applies anti-weight by generating compensating UP pulses that counterbalance the harmful effect of the pulse-width limited DN pulse. When the DN pulse is restricted in width, the control circuitry generates corresponding UP pulses with appropriate current and duration to supply the charges that were not removed, creating a counterweight that restores charge balance and enables complete phase error cancellation.
Data Source
AI summary
A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.