PLL Charge Pump Topology for Low Static Phase Error
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Solution Overview
Problem
Clock skew and clock phase drifts in internal clock signals of programmable logic devices can cause data degradation and impair processing operations.
Innovation Solution
A phase-locked loop (PLL) circuit with a charge pump that includes pairs of source follower transistors to reduce leakage current and static charge errors, thereby improving phase alignment and reducing phase discrepancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional charge pump circuits are used in PLL, then the circuit can generate clock signals, but static phase error and phase drift occur due to leakage current and static charge accumulation
Solution Approach 1:
The patent extracts and removes the harmful leakage current paths from the charge pump circuit by implementing a dual charge pump architecture where one charge pump is actively pumping charge while the other is deactivated, preventing leakage accumulation during idle periods
Solution Approach 2:
The patent periodically discharges accumulated static charge from the charge pump nodes through controlled switching, discarding the harmful static charge buildup while recovering the useful clock signal generation function in the next pumping cycle
2Productivity
If charge pump leakage current is not reduced, then the circuit operation is simple, but clock phase drift and data degradation occur
Solution Approach 1:
The patent implements periodic charge pumping cycles where the charge pump alternates between active pumping phases and inactive discharge phases, creating a periodic action that prevents continuous leakage current accumulation while maintaining average low power consumption
Solution Approach 2:
The patent performs preliminary discharge of leakage charge during the inactive phase before the next pumping cycle begins, preventing leakage current from accumulating to harmful levels during operation
3Reliability
If static charge errors are not compensated, then the circuit design is simpler, but phase discrepancy and clock skew increase
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector continuously monitors phase differences and adjusts the charge pump operation accordingly, creating a closed-loop system that compensates for static charge errors and maintains precise phase alignment
Data Source
AI summary
This disclosure relates to a phase-locked loop (PLL) of a programmable logic device (PLD) (e.g., a field programmable gate array (FPGA)) with reduced static phase error (SPE). The PLD may perform various operations using an internal clock signal generated by the PLL. The PLL may include a charge pump maintaining a phase alignment of the internal clock signal based on a reference clock signal. The charge pump may include a first pair of source follower transistors to reduce the leakage current when the charge pump is deactivated. Alternatively or additionally, the charge pump may include a second pair of source follower transistors to reduce a differential voltage between internal nodes and an output terminal when the charge pump is activated. As such, the charge pump may generate the internal clock signal with reduced SPE and/or phase drift based on including the first and/or second pair of source follower transistors.