PLL Charge Pump Pre-Charging for Lower Jitter and Power
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Solution Overview
Problem
Closed-loop clock signal generators, such as PLLs, experience jitter due to voltage level differences between control nodes and current source/sink nodes, leading to performance limitations and increased power consumption in maintaining equal voltage levels.
Innovation Solution
A charge pump circuit with transconductance devices pre-charges circuit nodes to voltage levels closer to the control node, reducing voltage differences and minimizing charge sharing, thereby reducing jitter and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage levels of current source/sink nodes are maintained equal to control node voltage, then jitter is reduced, but power consumption increases
Solution Approach 1:
The charge pump circuit pre-charges the current source and sink nodes to voltage levels that are preliminary adjusted relative to the control node voltage. This preliminary action reduces the voltage difference before the nodes are switched, thereby reducing jitter while avoiding continuous power consumption required to maintain equal voltage levels.
Solution Approach 2:
The patent changes the voltage parameters of the current source and sink nodes dynamically. Instead of maintaining fixed equal voltage levels, the nodes are charged to different voltage levels (first voltage for source node, second voltage for sink node) based on operational requirements, reducing both jitter and power consumption.
2Reliability
If complex Op Amp designs are used to maintain equal voltage levels, then jitter is reduced, but device complexity and die area increase
Solution Approach 1:
The patent extracts the complex Op Amp design from the charge pump circuit and replaces it with a simplified switching architecture. By removing the Op Amp component and using direct voltage level switching with transconductance devices, the circuit achieves jitter reduction without the complexity and die area overhead of Op Amp-based solutions.
Solution Approach 2:
Instead of using expensive and complex Op Amp circuits, the patent employs simpler, less costly switching elements and transconductance devices that achieve the same jitter reduction function with reduced complexity and smaller die area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces voltage fluctuations and jitter in the clock signal, enhancing performance while minimizing power consumption and die area, offering a more efficient alternative to complex Op Amp designs.
Implementation Method 1
The charge pump circuit may further includes a first transconductance device, coupled to the first circuit node, and configured to pre-charge the first circuit node to a voltage level based on a threshold voltage of the first transconductance device
Data Source
AI summary
An apparatus includes an oscillator circuit that may generate a clock signal with a frequency that is based on a voltage level of a control node, and a charge pump circuit that includes a first current source and a second current source. The first current source may be coupled between a first supply node and a first circuit node. The second current source may be coupled between a second supply node and a second circuit node. The charge pump circuit may be configured to pre-charge the first and second circuit nodes to voltage levels that differ from the control node and the first and second supply nodes. In addition, the charge pump circuit may select, based on phase information, either the first or second circuit node, and then modify, based on a voltage level of the selected circuit node, a voltage level of the control node.