PLL Charge Pump Circuit for High Swing and Fast Switching
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Solution Overview
Problem
Conventional PLL systems in radar systems face inefficiencies due to compromised switching time and voltage range of phase frequency detectors (PFD) and charge pumps (CP), leading to reduced accuracy in object detection and frequency matching.
Innovation Solution
A phase locked loop system with a PFD providing shifted UP pulses and a CP comprising switching transistors with high switching speed and constant gate bias transistors with high breakdown voltage, allowing for high signal swing and reduced reset delay, enhancing signal-to-noise ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional charge pump transistors are used with high breakdown voltage, then voltage range is improved, but switching speed deteriorates
Solution Approach 1:
The charge pump circuit is segmented into two distinct transistor sets: switching transistors (first set) with low breakdown voltage optimized for high-speed operation, and constant gate bias transistors (second set) with high breakdown voltage optimized for voltage range. This segmentation allows each transistor set to be independently optimized for its specific function, resolving the contradiction between switching speed and voltage range.
Solution Approach 2:
Different regions of the charge pump circuit are assigned different transistor characteristics tailored to local functional requirements. The switching transistors use low breakdown voltage devices for fast switching in the signal path, while the constant gate bias transistors use high breakdown voltage devices for stable voltage reference, achieving local optimization of both speed and voltage range.
2Loss of time
If PFD switching time is reduced, then frequency matching speed is improved, but voltage range of CP deteriorates
Solution Approach 1:
The circuit is segmented such that the PFD and switching transistors operate at low voltage for fast switching time, while the constant gate bias transistors provide high voltage range capability. This segmentation decouples the trade-off, allowing fast switching without sacrificing voltage range.
Solution Approach 2:
The constant gate bias transistors act as intermediaries that provide high voltage capability to the charge pump without directly affecting the fast switching operation of the PFD and switching transistors. They mediate between the low-voltage fast-switching domain and the high-voltage domain, resolving the contradiction.
Data Source
AI summary
According to an aspect, a phase locked loop system comprises a charge pump (CP) comprising a set of switching transistors and a set of non-switching transistor, in that the set of switching transistors operative at a low break down voltage and a high switching speed compared to that of the set of non-switching transistors, and comparative a voltage comprising a configured to generate a UP pulse when a first plurality of metal strips forming a first part of a closed contour enclosing a first area, and a phase frequency detector (PFD) providing a UP pulse swinging between a VDDL and a VDDH, wherein the PFD is interfaced with the CP such that, the UP pulse drives a first switching transistor in the CP to couple the VDDH to an output terminal through a first non-switching transistor that is biased for charge pump.