Fractional-N PLL Charge Summation for Transient Suppression
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Solution Overview
Problem
Phase-locked loops face limitations in fine frequency resolution due to integer division ratios, leading to transients from temporal mismatches between current pulses generated by PFD and DAC charge pumps, which affect the loop filter and VCO performance.
Innovation Solution
A phase-locked loop design that includes a summation unit to combine current pulses from PFD and DAC charge pumps, generating a single current pulse representative of the phase-difference and error caused by divisor variation, which is then filtered to produce a control signal for the signal generator, reducing transients and improving frequency stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a small reference frequency is used to achieve fine frequency resolution, then frequency resolution is improved, but the loop filter bandwidth must be narrowed to remove sidebands, which increases transition time and reduces operating speed
Solution Approach 1:
The patent segments the charge pump operation into multiple phases within each reference cycle: a first phase where charge is pumped in response to phase detection, and a second phase where additional charge is pumped to compensate for divisor variation effects. This segmentation allows the system to maintain fine frequency resolution with a small reference frequency while avoiding the need to narrow the loop filter bandwidth, thus preserving fast transition speed.
2Object-generated harmful factors
If the loop filter bandwidth is narrowed to remove sidebands caused by small reference frequency, then sideband suppression is improved, but transition time increases and VCO phase noise suppression decreases
Solution Approach 1:
The patent applies preliminary action by compensating for the divisor variation effects during the charge pump operation itself, before the signal passes through the loop filter. By pumping additional charge in a second phase to counteract the effects of divisor modulation, the system eliminates the need for narrow loop filter bandwidth to suppress sidebands, allowing the loop filter to maintain a wider bandwidth that enables fast transitions and effective phase noise suppression.
3Device complexity
If integer division ratios are used in the feedback loop, then circuit simplicity is maintained, but frequency resolution is limited to steps of at least the reference frequency
Solution Approach 1:
The patent changes the parameter being controlled from the division ratio itself to the charge pump output charge. By making the charge pump output charge variable while maintaining a fixed integer division ratio, the system achieves fine frequency resolution without changing the divider architecture. The variable charge injection compensates for the quantization effects of integer division, enabling frequency control finer than the reference frequency while keeping the circuit simple with standard integer dividers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances frequency stability and reduces transients, allowing for finer frequency resolution without the limitations of integer division ratios, thereby improving the phase-locked loop's performance and noise suppression capabilities.
Implementation Method 1
The summation unit receives the first and second current pulses and stores an electrical charge representative of those current pulses and the summation unit outputs a single current pulse dependent on the electrical charge stored by the summation unit
Data Source
AI summary
A phase-locked loop arranged to generate an output signal having a first frequency that is a static value times the frequency of a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a divider arranged to receive the output signal and divide the output signal to form a feedback signal, the divider being arranged to vary the divisor by which the output signal is divided to cause the output signal to have a frequency that is said static value times the frequency of the reference signal, a comparison unit arranged to compare the feedback signal with the reference signal, one or more current generators arranged to output current pulses in dependence on said comparison, a summation unit arranged to receive the current pulses output by the current generator(s) and form a single current pulse therefrom and a loop filter arranged to filter the single current pulse to form a control signal for controlling the signal generator, the phase-locked loop being arranged such that the current generator(s) generate(s) a first current pulse dependent on a phase-difference between the feedback signal and the reference signal and a second current pulse whose magnitude and sign are dependent on an error in the feedback signal that is caused by the variation of the divisor, and the summation unit receives the first and second current pulses and stores an electrical charge representative of those current pulses and the summation unit outputs a single current pulse dependent on the electrical charge stored by the summation unit, said single current pulse being representative of a phase-difference that would have existed between the reference signal and the feedback signal if the feedback signal had been formed by dividing the output signal by said static value and not by the varied divisor.