PLL Chirp-Interval Calibration for Faster Radar Frequency Lock
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional PLL circuits in automotive radar systems require lengthy calibration routines, which can only be performed at startup, leading to delayed frequency adjustments and reduced operational efficiency.
Innovation Solution
A PLL circuit with a tunable resonant circuit, phase-frequency detector, charge pump, filter, timer, and calibration circuit that enables dynamic calibration during the dead time between chirp signals, allowing for rapid frequency adjustments and compensation of temperature and process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional calibration techniques are used in PLL circuits, then frequency accuracy is improved, but calibration time increases significantly
Solution Approach 1:
The patent pre-calibrates the VCO by storing calibration data (mapping between control voltage and frequency) in a lookup table during manufacturing or initialization. During operation, the system performs rapid interpolation queries on this pre-computed data instead of performing lengthy real-time calibration, thus achieving accurate frequency adjustment without the time penalty of conventional calibration methods
Solution Approach 2:
The patent replaces the conventional iterative calibration process (which requires multiple PLL settling periods) with a computational approach using polynomial interpolation on pre-stored calibration data. This substitution of mechanical/iterative adjustment with mathematical computation dramatically reduces calibration time while maintaining frequency accuracy
2Productivity
If calibration is performed only at startup, then device complexity is reduced, but operational efficiency deteriorates
Solution Approach 1:
The patent transforms the static calibration approach (performed only at startup) into a dynamic system that can perform rapid frequency adjustments during operation. By using the lookup table with interpolation, the system can adapt to frequency requirements in real-time between chirp signals, converting a static calibration mechanism into a dynamic frequency adjustment capability
Solution Approach 2:
The patent utilizes the periodic dead time between consecutive chirp signals to perform frequency calibration and adjustment operations. This periodic opportunity structure allows the system to maintain frequency accuracy throughout operation without requiring continuous calibration, balancing operational efficiency with calibration needs
3Measurement precision
If PLL settling time is waited at each calibration step, then frequency accuracy is improved, but total calibration time increases
Solution Approach 1:
The patent performs the time-consuming PLL settling and frequency measurement operations in advance during manufacturing or initialization, storing the results in a lookup table. During operational calibration, the system only needs to perform rapid mathematical interpolation on this pre-acquired data, eliminating the need to wait for PLL settling at each calibration step while maintaining accuracy
Solution Approach 2:
The patent creates a simplified model (lookup table with polynomial interpolation) that replicates the complex PLL frequency-characteristic relationship. Instead of repeatedly interacting with the actual PLL system (which requires settling time), the system uses this copied model for rapid calibration decisions, achieving both speed and accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates fast and dynamic calibration of PLL circuits, enabling real-time frequency adjustments and improved accuracy by performing calibration between chirp signals, reducing the need for prolonged startup calibration and enhancing the radar system's responsiveness.
Implementation Method 1
A voltage-controlled oscillator (VCO) may be used in a FMCW radar detection system to generate variable frequency signals (e.g., to generate 'chirp' signals). The voltage-controlled oscillator may comprise a tunable LC resonant circuit.
Implementation Method 2
a phase-frequency detector circuit sensitive to an input reference signal and to the variable-frequency output signal and configured to generate a first digital control signal and a second digital control signal as a function of a timing offset of the variable-frequency output signal with respect to the input reference signal
Implementation Method 3
a charge pump circuit and a filter circuit configured to generate the control signal as a function of the first digital control signal and the second digital control signal
Implementation Method 4
a timer circuit sensitive to a reset signal and configured to generate a timing signal, wherein the timing signal is asserted in response to a pulse sensed in the reset signal and de-asserted after a time interval from the sensed pulse
Data Source
AI summary
A PLL has a tunable resonator including an inductance and variable capacitance coupled between first and second nodes, and capacitances coupleable between the nodes. A control node is coupled to the variable capacitance and receives a control signal for tuning the resonator. A biasing circuit biases the resonator to generate an output. A PFD circuit senses timing offset of the output with respect to a reference and asserts first or second digital signals dependent on the sign of the timing offset. A charge pump generates the control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and de-asserts the timing signal after a time interval. A calibrator couples selected capacitances between the first and second nodes as a function of the second digital signal, in response to assertion of the timing signal.