PLL Frequency Synthesizer With Forward-Path Chirp Modulation
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Solution Overview
Problem
Phase-locked loop (PLL)-based frequency synthesizers face challenges in generating chirp signals with high chirp rates while maintaining low phase noise, particularly due to limitations in analog PLL circuits and conventional digital PLL circuits using binary phase detectors.
Innovation Solution
The techniques involve modulating the amplitude of the forward path signal in a PLL circuit based on a control signal with a profile determined by the target frequency, allowing for the generation of signals with steep frequency profiles and high chirp rates while using a low slew rate PLL loop filter to maintain low phase noise, and employing digital PLL architectures with binary phase detectors to reduce power consumption and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high slew rate PLL loop filter is used to generate signals with steep frequency profiles (high chirp rate), then the frequency profile steepness is improved, but the phase noise increases
Solution Approach 1:
The patent segments the frequency modulation function into two independent parts: the PLL loop filter handles only phase noise suppression with low slew rate, while a separate forward path modulator handles the steep frequency profiling. This segmentation allows each component to be optimized for its specific function without compromising the other.
Solution Approach 2:
The patent introduces a forward path modulator as an intermediary component that injects the frequency profile directly into the forward signal path. This mediator enables the system to achieve high chirp rates without requiring the PLL loop filter to have high slew rate, thus maintaining low phase noise while achieving steep frequency profiles.
2Speed
If analog PLL circuits are used to generate high chirp rate signals, then the frequency profile steepness is improved, but the circuit complexity and power consumption increase
Solution Approach 1:
The patent replaces complex analog PLL circuits with a simplified digital PLL architecture. The frequency profiling function, which would traditionally require complex analog modulation circuits, is instead implemented through digital signal processing in the forward path, reducing overall circuit complexity while maintaining high chirp rate capability.
3Productivity
If the PLL loop filter slew rate is increased to achieve high chirp rates, then the frequency modulation speed is improved, but the phase noise performance deteriorates
Solution Approach 1:
The patent makes the forward path signal dynamic by modulating it with a time-varying profile that corresponds to the desired frequency profile. This dynamic modulation in the forward path enables high frequency modulation speed without requiring the PLL loop filter to operate at high slew rates, thereby preserving phase noise performance.
Data Source
AI summary
This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise.