PLL Circuit Clock Abnormality Detection for Image Data Processing
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Solution Overview
Problem
Existing data processing devices struggle with maintaining normal operation when noise affects the clock signal during data transmission, leading to incomplete or abnormal image data processing, which can cause system stalls and reduced image quality.
Innovation Solution
A data processing device equipped with a PLL circuit to detect clock abnormalities using an internal clock different from the external clock, allowing it to stop data processing during noise occurrences and resume when the clock stabilizes, thereby reducing the impact of noise on data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is deleted during periods when noise is detected in the clock signal, then abnormal data processing is prevented, but data processing continuity deteriorates and system productivity decreases
Solution Approach 1:
The system performs preliminary detection of clock signal abnormalities using the PLL circuit before abnormal data is processed. By detecting lock state changes in advance, the system can prepare appropriate responses (deletion or pause) to prevent abnormal data from affecting downstream processing, thus maintaining reliability without unnecessary data loss
Solution Approach 2:
The system dynamically switches between two operational modes: deleting abnormal data when noise occurs frequently, and pausing data intake when lock state changes are detected. This dynamic adaptation allows the system to optimize between reliability and productivity based on the actual noise conditions and type of abnormality detected
2Stability of the object's composition
If the external clock signal is used for synchronization, then data processing synchronization is maintained, but noise from the external clock causes abnormality detection failure
Solution Approach 1:
The PLL circuit serves as an intermediary between the external clock signal and the data processing system. It receives the noisy external clock and generates a cleaned internal clock signal that is free from noise while maintaining synchronization with the original signal. This intermediary approach allows the system to use the external clock for synchronization without directly exposing downstream circuits to noise
Solution Approach 2:
The system creates a copy of the external clock signal through the PLL circuit, generating an internal clock that replicates the timing characteristics of the external clock but is free from noise. This copied clock signal is then used for synchronization and abnormality detection, eliminating the harmful effects of noise while preserving synchronization stability
3Measurement precision
If a PLL circuit is added to detect clock abnormalities, then noise detection capability is improved, but device complexity increases
Solution Approach 1:
The PLL circuit performs multiple functions: it generates the internal clock signal for data processing, detects clock abnormalities through lock state monitoring, and provides synchronization. By making the PLL circuit multi-functional, the system achieves precise abnormality detection without adding separate dedicated detection circuits, thus limiting the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces the influence of noise on data processing, preventing system stalls and maintaining image quality by detecting and managing clock abnormalities, ensuring stable data processing even with noisy external clock signals.
Implementation Method 1
a PLL circuit to receive the external clock
Data Source
AI summary
A data processing device comprises: a data receiver to receive data to be processed, an external clock, and a unit control signal determining a processing unit for the data to be processed from an outside, the data receiver including a PLL circuit to receive the external clock; a clock abnormality detector to operate based on a clock of a system different from a system of the external clock and detect abnormality of the external clock based on a lock signal output from the PLL circuit; and a data processing controller to control processing of the data. When abnormality of the external clock is detected, the data processing controller stops taking in the data to be processed, and when the external clock becomes normal again, take in the unit control signal and resume taking in the data to be processed.