PLL Realignment Circuit Using Skew-Matched Clock Alignment
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Solution Overview
Problem
Phase locked loops (PLLs) used in high-speed clock signal generation can exhibit anomalous behavior due to phase noise and spurious signals, leading to suboptimal output from voltage-controlled oscillators (VCOs) over time, which can break the locking condition and require periodic realignment.
Innovation Solution
A phase locked loop with a realignment path that generates accurately timed clock realignment signals using charge pump-based realignment and matching skew mitigation circuitry, including identical logic gates to maintain alignment with the current state of the VCO and PLL, avoiding the need for programmable delay lines or delay lock loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a PLL is used for high-speed clock signal generation, then frequency stability is improved, but phase noise and spurious signals cause anomalous behavior over time
Solution Approach 1:
The patent implements periodic realignment of the VCO phase to the reference signal phase at predetermined intervals. This periodic action resets accumulated phase errors and prevents anomalous behavior from degrading the locking condition, thereby maintaining reliability over time while preserving frequency stability.
Solution Approach 2:
The patent uses a phase detector to continuously monitor the phase difference between the VCO output and reference signal, and feeds this information back to adjust the VCO phase periodically. This feedback mechanism detects and corrects phase noise and spurious signals, maintaining both stability and reliability.
2Reliability
If realignment is performed to maintain locking condition, then reliability is improved, but timing misalignment causes phase errors
Solution Approach 1:
The patent performs preliminary alignment of the realignment signal timing with the VCO clock cycle before executing the realignment. By pre-synchronizing the timing using the locked VCO frequency and phase information, the system ensures that the realignment operation occurs at the optimal moment, minimizing phase errors while maintaining reliability.
Solution Approach 2:
The patent replaces complex programmable delay lines and delay lock loops with a simplified timing mechanism that uses the already-locked VCO signals to automatically determine realignment timing. This substitution reduces complexity while maintaining precise phase alignment through the natural synchronization of the locked PLL.
3Measurement precision
If skew mitigation circuitry is added to improve timing alignment, then phase alignment accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the skew mitigation function into the existing realignment path by using the same phase detector and control logic that are already present in the locked PLL. Instead of adding separate skew correction circuits, the system utilizes and combines existing components to achieve timing alignment, thereby improving phase alignment accuracy without significantly increasing device complexity.
Solution Approach 2:
The patent implements self-aligning circuitry that automatically adjusts timing using the locked VCO signals themselves. The system uses its own operational signals to determine and correct timing skew, eliminating the need for external programmable delay lines or separate delay lock loops, thus maintaining low complexity while achieving high alignment accuracy.
Data Source
AI summary
Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.