PLL Clock Power Control Using BER Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase locked loop (PLL) circuits face challenges in maintaining power efficiency as the noise characteristics of the signal change, leading to decreased power efficiency due to fixed power control.
Innovation Solution
An apparatus and method for generating a clock that includes a phase locked loop circuit, a monitoring circuit to monitor the bit error rate of a signal, and a control logic circuit that adjusts the power applied to the PLL circuit based on the signal quality, by connecting or disconnecting boosting current sources and controlling the gain of a loop filter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power for controlling the phase locked loop circuit is fixed, then the noise characteristics of the signal can be controlled, but the power efficiency decreases when signal noise characteristics change
Solution Approach 1:
The patent implements dynamic power control by adjusting the current magnitude supplied to the phase locked loop circuit based on monitored signal quality (bit error rate). When signal quality degrades below a threshold, the current magnitude is increased to improve noise characteristics. When signal quality is good, the current magnitude is decreased to save power. This dynamic adjustment resolves the contradiction between maintaining reliable noise control and achieving power efficiency.
Solution Approach 2:
The patent employs a feedback mechanism where the bit error rate of the received signal is continuously monitored and used to control the power supply to the phase locked loop circuit. The control logic circuit receives the bit error rate information and adjusts the current magnitude accordingly, creating a closed-loop system that adapts power consumption to actual signal conditions, thereby resolving the contradiction between fixed power control and adaptive power efficiency.
2Reliability
If the current magnitude for the phase locked loop circuit is increased to improve noise characteristics, then signal quality improves, but power consumption increases
Solution Approach 1:
The patent changes the current magnitude parameter of the phase locked loop circuit based on signal quality conditions. By monitoring the bit error rate and adjusting the current magnitude accordingly, the system optimizes the balance between signal quality and power consumption. The current magnitude is increased only when necessary (when bit error rate exceeds threshold) and decreased when signal quality is good, resolving the contradiction between improving signal quality and reducing power loss.
Solution Approach 2:
The patent implements periodic monitoring of the bit error rate and periodic adjustment of the current magnitude to the phase locked loop circuit. This periodic control action allows the system to adapt to changing signal conditions while minimizing unnecessary power consumption during periods of good signal quality, thereby resolving the contradiction between continuous signal quality improvement and energy loss reduction.
3Use of energy by moving object
If the current magnitude for the phase locked loop circuit is decreased to reduce power consumption, then power efficiency improves, but noise characteristics deteriorate
Solution Approach 1:
The patent implements dynamic power control where the current magnitude is adjusted in real-time based on monitored signal quality. When signal quality is good (bit error rate below threshold), the current magnitude is decreased to improve power efficiency. When signal quality deteriorates, the current magnitude is increased to maintain acceptable noise characteristics. This dynamic adjustment resolves the contradiction between power efficiency and noise characteristics.
Solution Approach 2:
The patent employs a feedback mechanism where the bit error rate is continuously monitored and used to control the current magnitude supplied to the phase locked loop circuit. This feedback control ensures that power consumption is reduced only when signal quality permits, and noise characteristics are maintained when signal quality degrades, thereby resolving the contradiction between power efficiency improvement and noise characteristic deterioration.
Data Source
AI summary
An example apparatus for generating a clock includes a phase locked loop circuit to generate a first clock signal having a specified frequency through an oscillator, a monitoring circuit to monitor a first bit error rate (BER) of a first signal received in response to the first clock signal, and a control logic circuit to control the phase locked loop circuit based on a monitoring result. The control logic circuit is to connect a first boosting current source, which is included in the phase locked loop circuit, with the oscillator, when the first bit error rate is equal to or greater than a preset threshold value, and disconnect a second boosting current source, which is previously connected with the oscillator, from the oscillator, when the first bit error rate is less than the threshold value.