PLL Clock Buffer Spread Spectrum Modulation Without Cycle Slip
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Solution Overview
Problem
Conventional controllable delay clock buffers do not effectively reduce Electromagnetic Interference (EMI) and fail to maintain spread spectrum modulation without causing cycle slip, which is critical for synchronized clock signals in digital devices.
Innovation Solution
A controllable delay clock buffer that incorporates a Phase-Locked Loop (PLL) with injected spread spectrum modulation into the PLL loop filter, using a secondary charge pump to generate a current signal that integrates into the loop filter, allowing for frequency modulation without distorting the signal and ensuring zero cycle slip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If spread spectrum modulation is applied to reduce EMI, then electromagnetic interference is reduced, but cycle slip occurs in the clock signal
Solution Approach 1:
The patent introduces a phase detector as an intermediary component between the PLL and the spread spectrum modulated output. This phase detector continuously monitors the phase relationship between the input clock and output clock, detecting phase errors caused by spread spectrum modulation and generating correction signals to prevent cycle slip, thus mediating between EMI reduction and signal reliability
Solution Approach 2:
The patent implements a feedback mechanism where the output clock is fed back through a phase detector that compares its phase with the input clock. The phase error signal is fed back to adjust the PLL control, creating a closed-loop system that automatically corrects phase deviations and prevents cycle slip while maintaining spread spectrum modulation benefits
2Object-affected harmful factors
If spread spectrum modulation is maintained ON at all outputs, then EMI reduction is achieved, but the minimum delay between input and output increases
Solution Approach 1:
The patent applies dynamics by making the spread spectrum modulation controllable and adjustable rather than permanently fixed. The modulation depth and frequency can be dynamically adjusted based on operational requirements, allowing the system to optimize between EMI reduction and delay performance by adapting the modulation parameters in real-time
3Device complexity
If conventional controllable delay buffers are used, then device complexity is low, but EMI reduction capability is absent
Solution Approach 1:
The patent merges the PLL-based controllable delay buffer functionality with spread spectrum modulation capability into a single integrated device. By combining these two functions that were previously separate, the patent achieves both EMI reduction and precise delay control without requiring multiple discrete components, thus resolving the contradiction between device complexity and EMI reduction capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides spread spectrum modulation with zero cycle slip, effectively reducing EMI by controlling the frequency and amplitude of the modulation signal, ensuring phase alignment and minimizing edge wandering, thus enhancing the reliability of clock signals in digital devices.
Implementation Method 1
The programmable current waveform is integrated by one of the loop filter capacitors to create a waveform that effectively varies the input to the VCO of the PLL to define a frequency modulation profile
Data Source
AI summary
A controllable delay clock buffer that provides spread spectrum modulation of the output signals with zero cycle slip includes a PLL having a PLL loop filter that comprises an RC network. A clock signal is input to the PLL, and a SS modulation frequency is injected into the capacitor of the PLL loop filter. The SS signal is provided by a secondary charge pump that produces a programmable waveform such as a square wave or a stair case square wave current signal. The programmable waveform is integrated by the loop filter capacitor to form a corresponding triangular or trigonal waveform which varies the input to the VCO of the PLL to define a frequency modulation profile that has a corresponding triangular or trigonal envelope. The bandpass profile of the SS modulation signal is at a higher frequency range than the lowpass profile of the PLL, so that the SS waveform profile is not distorted or cancelled by the PLL.