PLL Clock Calibration for Unknown Reference Frequencies
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Solution Overview
Problem
Conventional electronic devices face challenges in generating a clock signal when the frequency of the reference clock from an unknown host device is unknown, potentially leading to synchronization issues.
Innovation Solution
A semiconductor integrated circuit with a calibration circuit and phase locked loop circuit that adjusts the base oscillation frequency of a voltage-controlled oscillator using a calibration code, allowing for detection and synchronization with the reference clock signal, even when its frequency is unknown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the electronic device uses a standardized reference clock signal (19.2 MHz, 26 MHz, 38.4 MHz, 52 MHz) for clock signal generation, then the clock signal generation is reliable when connected to known host devices, but the electronic device cannot properly generate clock signals when connected to unknown host devices with unknown reference clock frequencies
Solution Approach 1:
The voltage-controlled oscillator is designed to operate across a wide frequency range (10 MHz to 100 MHz) and can be tuned to match any reference clock frequency from unknown host devices. The same oscillator circuit serves both as the clock signal generator and as the frequency matching element, eliminating the need for separate frequency detection and adjustment circuits.
Solution Approach 2:
The phase difference between the clock signal and reference clock signal is detected and fed back to the voltage-controlled oscillator through the phase locked loop circuit. This feedback mechanism automatically adjusts the oscillator's output frequency to match the reference clock frequency, enabling the device to adapt to unknown host devices without requiring manual configuration or complex detection circuits.
2Measurement precision
If the electronic device attempts to detect the frequency of the reference clock signal from an unknown host device, then the clock signal can be properly synchronized, but the detection process increases the circuit complexity
Solution Approach 1:
The frequency detection function is merged into the phase locked loop circuit itself. The phase difference detection mechanism inherently provides frequency information, as the oscillator automatically adjusts its frequency to eliminate the phase difference. This merging eliminates the need for separate frequency detection circuits while maintaining accurate frequency measurement capability.
Solution Approach 2:
The voltage-controlled oscillator performs self-adjustment of its frequency based on the phase difference feedback from the phase locked loop circuit. The system automatically detects and corrects frequency mismatches without requiring external frequency detection equipment or complex measurement circuits, achieving accurate frequency detection through the oscillator's own feedback mechanism.
Data Source
AI summary
A semiconductor integrated circuit includes: a node to receive a reference clock signal; a voltage-controlled oscillation circuit to generate a clock signal based on a code corresponding to a frequency of the reference clock signal received by the node and on a control voltage; a calibration circuit to generate the code based on the frequency of the reference clock signal and on a frequency of the clock signal, and supply the generated code to the voltage-controlled oscillation circuit; and a phase locked loop circuit to generate the control voltage based on a phase difference of the clock signal with respect to the reference clock signal, and supply the generated control voltage to the voltage-controlled oscillation circuit. The voltage-controlled oscillation circuit is capable of changing the frequency of the clock signal based on the code supplied from the calibration circuit and on the control voltage supplied from the phase locked loop circuit.