PLL Differential Clock Buffering with Common-Mode Equalization
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Solution Overview
Problem
Zero-delay clock generators for differential clocks face challenges with common-mode voltage drift, leading to phase offsets and skew issues due to differences in common-mode voltages between reference and feedback clocks, which disrupt the synchronization of clocks in high-speed digital systems.
Innovation Solution
Incorporating a common-mode sense and equalizer that senses the common-mode voltage differences between the reference and feedback clocks and adjusts the delays through differential buffers to match the common-mode voltages, thereby reducing phase offsets and ensuring accurate clock synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential clocks are used in zero-delay clock generators, then signal noise and distortion are reduced, but common-mode voltage drift causes phase offsets and clock skew
Solution Approach 1:
A common-mode sense and equalizer circuit is introduced as an intermediary component between the differential clock inputs and the PLL. This circuit senses the common-mode voltages of the reference and feedback clocks and generates equalizing signals to adjust the delay buffers, thereby eliminating phase offsets caused by common-mode voltage differences without affecting the noise-rejection benefits of differential signaling
Solution Approach 2:
The common-mode sense and equalizer implements a feedback mechanism by continuously monitoring the common-mode voltages of the reference and feedback clocks and dynamically adjusting the delay buffer settings. The equalizer uses the sensed common-mode voltage differences to generate control signals that feed back to the delay buffers, creating a closed-loop system that automatically compensates for common-mode drift
2Manufacturing precision
If common-mode voltage differences exist between reference and feedback clocks, then phase offsets occur, but adding equalizer circuitry increases system complexity
Solution Approach 1:
The common-mode sense and equalizer functionality is merged with the existing delay buffer circuitry. The equalizer shares common circuit elements and control pathways with the buffer system, integrating the complexity into a unified structure rather than adding completely separate components. This merging approach minimizes the overall increase in system complexity while achieving phase matching
Data Source
AI summary
A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.