PLL-Based Clock Delay Adjustment for PVT-Independent I/O Testing
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Solution Overview
Problem
High-speed digital I/O circuit testing equipment is expensive and typically separate from the device under test, and unit delay cells in test circuits are dependent on process, voltage, and temperature (PVT), making them PVT-dependent.
Innovation Solution
A phase-locked loop system comprising an N-divider, phase frequency detector, charge pump, loop filter, voltage controlled oscillator, and adjustable delay element that generates a blended delay signal based on a clock signal and voltage control signal, making the delay independent of PVT.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional separate testing equipment is used for high-speed I/O circuits, then testing capability is achieved, but cost increases and integration is lost
Solution Approach 1:
The patent combines the testing function with the device under test by integrating a phase-locked loop circuit directly into the memory device. This allows the memory device to perform self-testing at high speeds (e.g., 6 Gbps) without requiring separate external testing equipment, thereby reducing cost while maintaining testing capability through the integrated PLL-based delay adjustment mechanism
2Adaptability or versatility
If PVT-dependent delay cells are used in test circuits, then delay adjustment is achieved, but PVT independence is lost
Solution Approach 1:
The patent employs a phase-locked loop with feedback control to achieve PVT-independent delay adjustment. The PLL continuously monitors the phase and frequency between the reference clock and the delayed clock, and automatically adjusts the delay element to maintain accurate delay values despite PVT variations. This feedback mechanism eliminates the PVT-dependency of traditional delay cells while preserving delay accuracy
3Speed
If high-speed testing is implemented, then data rate capability is improved, but jitter increases
Solution Approach 1:
The patent uses a dynamic delay adjustment mechanism controlled by the phase-locked loop that can adapt in real-time to maintain optimal performance at high data rates. The PLL continuously tunes the delay element to compensate for high-speed effects, enabling accurate delay adjustment at 6 Gbps and beyond while maintaining low jitter through active control rather than static fixed delays
Data Source
AI summary
A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal. In a phase frequency detector, a control signal is generated in accordance with a phase difference and a frequency difference between the output clock signal and a feedback signal generated by a voltage controlled oscillator coupled to the phase frequency detector. The control signal is then fed through a charge pump and a loop filter to generate a voltage control signal according to the control signal. Moreover, in an adjustable delay element, a blended delay signal is generated according to a clock signal and the voltage control signal.