Fractional-N PLL Clock Dithering for Delta-Sigma Noise Control
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) in cellular telephone receivers and transmitters face interference issues due to digital noise generated by delta-sigma modulators, which conventional isolation techniques are not entirely effective in eliminating, especially at high frequencies.
Innovation Solution
A programmable clock dithering circuit is introduced to dither the phase of the clock signal supplied to the delta-sigma modulator, either pseudo-randomly or rotationally, to spread or shift the noise power, reducing interference with other circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional isolation techniques are used to reduce digital noise interference, then circuit isolation is improved, but the techniques are not entirely effective especially at high frequencies
Solution Approach 1:
The patent converts the harmful digital noise from the delta-sigma modulator into a beneficial effect by using dithering techniques. The noise is deliberately modulated to spread its spectral energy, transforming it from a concentrated harmful interference into a distributed signal that can be more easily filtered or managed, thereby improving overall system performance
2Object-affected harmful factors
If the clock signal phase is dithered pseudo-randomly, then noise power is spread over frequency band reducing interference, but device complexity increases
Solution Approach 1:
The patent changes the temporal parameters of the clock signal by introducing phase dithering with pseudo-random variations. This modifies the clocking sequence to spread noise energy across frequency bands, achieving noise reduction through parameter modulation rather than through complex structural changes
3Object-affected harmful factors
If the clock signal phase is dithered rotationally, then noise power is shifted in frequency reducing interference, but device complexity increases
Solution Approach 1:
The patent employs periodic rotational dithering where the clock phase is systematically rotated through a sequence of predetermined angles. This periodic phase rotation shifts noise power to different frequency locations in a controlled manner, achieving spectral redistribution through repetitive cyclic action
Data Source
AI summary
The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.