PLL Reference Clock Divider for Stable SoundWire Frequency Changes
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Solution Overview
Problem
The SoundWire protocol's dynamic change in interface clock frequency can cause the phase-locked loop (PLL) in peripheral devices to temporarily lose phase-lock, resulting in undesirable audio artifacts like 'pops' and 'clicks' due to sudden changes in the reference clock frequency.
Innovation Solution
Incorporating a reference clock generator with a programmable clock divider that maintains a constant frequency for the PLL's reference clock, even when the interface clock frequency changes, by dynamically adjusting the divide ratio based on values stored in registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the interface clock frequency is dynamically changed during run-time, then the adaptability of the audio interface is improved, but the stability of the PLL phase-lock is deteriorated
Solution Approach 1:
A reference clock generator is introduced as an intermediary component between the interface clock and the PLL. This generator receives the dynamic interface clock and produces a stabilized reference clock output that maintains constant frequency regardless of interface clock changes. The PLL then locks to this stable reference clock rather than the variable interface clock, resolving the contradiction between dynamic adaptability and phase-lock stability.
Solution Approach 2:
The clock signal path is segmented into distinct functional stages: the interface clock stage for dynamic frequency control, the reference clock generator stage for frequency stabilization, and the PLL stage for phase-locking. By separating the frequency control function from the phase-locking function, the system can dynamically change interface clock frequency without affecting PLL stability.
2Adaptability or versatility
If the reference clock frequency changes suddenly, then the interface clock adaptability is improved, but audio artifacts are generated
Solution Approach 1:
The reference clock generator acts as a mediator that buffers the interface clock from the PLL. When interface clock frequency changes occur, the reference clock generator absorbs these changes and maintains a constant reference clock output, preventing sudden frequency transitions that would cause audio artifacts like pops and clicks.
Solution Approach 2:
The reference clock generator provides beforehand cushioning by pre-stabilizing the clock signal before it reaches the PLL. This cushioning effect protects the audio processing chain from abrupt frequency changes, ensuring smooth transitions and preventing harmful audio artifacts.
Data Source
AI summary
A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.