PLL Reference Clock Divider for Stable SoundWire Frequency Switching
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Solution Overview
Problem
The MIPI SoundWire protocol's dynamic change in interface clock frequency can cause temporary loss of phase-lock in peripheral devices, leading to undesirable audio artifacts like 'pops' and 'clicks' due to sudden changes in the reference clock frequency.
Innovation Solution
Incorporating a reference clock generator with a programmable clock divider that maintains a constant frequency for the PLL's reference clock, even when the interface clock frequency changes, by dynamically adjusting the divide ratio based on stored values, thereby preventing phase-lock loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the interface clock frequency is dynamically changed during run-time, then the adaptability of the audio interface is improved, but the stability of the PLL phase-lock is degraded
Solution Approach 1:
The patent introduces a reference clock generator as an intermediary component between the interface clock and the PLL. This generator receives the variable frequency interface clock and produces a stable reference clock signal with constant frequency, thereby mediating the conflict between frequency adaptability and phase-lock stability. The reference clock generator acts as a buffer that isolates the PLL from direct frequency changes.
Solution Approach 2:
The patent changes the frequency parameter of the reference clock generated by the reference clock generator based on the interface clock frequency changes. When the interface clock frequency changes, the reference clock generator adjusts its output frequency accordingly while maintaining a constant frequency ratio relationship, thus adapting to frequency changes without causing PLL instability.
2Adaptability or versatility
If the reference clock frequency changes suddenly, then the interface clock adaptability is improved, but harmful audio artifacts are generated
Solution Approach 1:
The patent implements beforehand cushioning by having the reference clock generator pre-adjust its output frequency in response to interface clock frequency changes before they reach the PLL. This gradual, controlled frequency adjustment prevents sudden frequency transitions that would cause audible pops and clicks, cushioning the impact of frequency changes on the audio output.
Solution Approach 2:
The reference clock generator serves as a mediator that filters and smooths frequency transitions. It receives the interface clock signal and generates a reference clock with controlled frequency changes, preventing direct transmission of abrupt frequency variations to the PLL and subsequent audio stages, thereby eliminating harmful audio artifacts.
3Reliability
If a programmable clock divider is used to maintain constant reference clock frequency, then the PLL phase-lock stability is improved, but the device complexity increases
Solution Approach 1:
The reference clock generator is designed to perform multiple functions: it divides the interface clock frequency, generates a stable reference clock signal, and adapts to different frequency conditions. By consolidating these functions into a single multi-functional module, the patent reduces overall system complexity while maintaining PLL stability.
Solution Approach 2:
The patent employs a programmable clock divider that can dynamically adjust its division ratio based on interface clock frequency changes. This dynamic adaptability allows the reference clock generator to maintain constant output frequency without requiring complex hardwired circuits, achieving stability through flexible, programmable control logic.
Data Source
AI summary
A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.