PLL Clock Synthesizer With Integrated Duty Cycle and Phase Control
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Solution Overview
Problem
Existing methods for correcting duty cycle errors in clock signals are slow and power-intensive, requiring complex circuits and taking hundreds of clock cycles to achieve accuracy, which is inadequate for modern system clock speeds.
Innovation Solution
A Duty Cycle Corrected Phase Interpolator (DCCPI) circuit that adjusts both phase and duty cycle of a clock signal in a single loop using a Phase Locked Loop (PLL), Digital Control Delay Line (DCDL), and voltage/current alternator, allowing for rapid correction of duty cycle to 50% using analog and digital controls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If iterative adjustment of delays is used to correct duty cycle error, then duty cycle accuracy is improved, but correction time increases significantly
Solution Approach 1:
The patent pre-calculates and stores optimal delay values in a lookup table before operation. When duty cycle correction is needed, the system directly retrieves the pre-computed delay value instead of performing iterative adjustments, achieving both high accuracy and fast correction speed simultaneously
Solution Approach 2:
The patent pre-calculates and stores optimal delay values in a lookup table before operation. When duty cycle correction is needed, the system directly retrieves the pre-computed delay value instead of performing iterative adjustments, achieving both high accuracy and fast correction speed simultaneously
2Measurement precision
If iterative delay adjustment circuits are used for duty cycle correction, then duty cycle control is achieved, but circuit complexity increases
Solution Approach 1:
The patent combines the delay adjustment function and duty cycle correction function into a single integrated circuit module. This merging eliminates the need for separate iterative adjustment circuits while maintaining precise duty cycle control capability
Solution Approach 2:
The patent uses a lookup table that stores pre-computed correction values. Instead of implementing complex real-time calculation circuits, the system copies the appropriate correction value from the lookup table based on the measured error, significantly reducing circuit complexity
3Measurement precision
If iterative duty cycle correction operations are performed, then duty cycle accuracy is improved, but power consumption increases
Solution Approach 1:
The patent pre-calculates optimal delay values and stores them in a lookup table during manufacturing or initialization. During operation, the system only needs to retrieve and apply the pre-computed value, avoiding continuous iterative calculations and significantly reducing power consumption while maintaining high accuracy
Solution Approach 2:
The system uses the measured duty cycle error to directly index into the lookup table and retrieve the corresponding correction value. This self-service approach eliminates the need for power-intensive iterative adjustment mechanisms while achieving accurate correction
Data Source
AI summary
A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.