PLL Clock Edge Filtering for Disturbance-Robust Timing
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Solution Overview
Problem
Existing systems face challenges in robustly filtering unwanted signals from clock signals, particularly in distributed systems, where external oscillator circuits can introduce disturbances leading to logic malfunctions and system crashes, and existing solutions like PLL circuits are not robust enough to handle these disturbances effectively.
Innovation Solution
A circuit arrangement using a Phase Lock Loop (PLL) circuit with a detector to identify correct edges in the clock signal, removing incorrect edges and providing a filtered clock signal, which includes a frequency multiplier, phase detector, voltage-controlled oscillator, and a window generator to ensure accurate timing without phase inaccuracies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a PLL circuit is used as the time base for the microcontroller and an external oscillator circuit is used as the time base for the peripheral devices, then the distributed system can handle different time base domains, but additional circuitry is required and the system remains not robust against clock disturbances
Solution Approach 1:
The patent introduces a detector circuit as an intermediary between the PLL output and the microcontroller. This detector monitors the clock signal edges and identifies when the PLL is locked, generating a ready signal without requiring additional complex circuitry. The detector acts as a mediator that translates PLL status into a simple binary ready state.
Solution Approach 2:
The system uses the existing PLL circuit's own output signal to generate the ready indication. The PLL output is fed back to the detector, which monitors the signal itself to determine lock status. This self-service approach eliminates the need for external monitoring circuits or additional time base domain handling infrastructure.
2Productivity
If external oscillator circuits are used to clock microcontrollers, then the system can perform functions such as climate control and window lift control, but electromagnetic disturbances can produce unwanted signals or spikes on the clock signal causing logic to malfunction
Solution Approach 1:
The patent applies beforehand cushioning by using the PLL circuit to pre-filter and stabilize the clock signal before it reaches the microcontroller. The PLL's inherent filtering characteristics cushion the microcontroller against electromagnetic disturbances and spikes in the external oscillator output, preventing logic malfunctions before they occur.
Solution Approach 2:
The detector circuit implements feedback by continuously monitoring the PLL output signal and generating a ready signal that indicates when the PLL has successfully locked onto the clock frequency. This feedback mechanism allows the system to respond to clock signal quality in real-time, ensuring reliable operation even in the presence of disturbances.
3Object-affected harmful factors
If analog filters are used to act as delays in the clock filter circuit, then the circuit can remove unwanted signals from the clock signal, but due to variations of such analog filters over temperature and voltage the circuit does not provide sufficient robustness
Solution Approach 1:
The patent replaces the mechanical/analog filter delay system with a digital logic-based delay mechanism. Instead of relying on analog RC time constants that vary with temperature and voltage, the invention uses digital counters and logic circuits that provide stable, predictable delays independent of environmental conditions. This substitution of mechanical/analog systems with digital systems eliminates the robustness problem.
Data Source
AI summary
A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.