Multi-Phase PLL Clock Noise Reduction via Fractional Delay Division
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Solution Overview
Problem
Existing clock signal noise reduction methods in frequency dividers result in significant noise in output clock signals, which affects the performance of connected radio frequency integrated circuits.
Innovation Solution
A clock signal noise reduction device and method that involves a phase generator, phase selector, and frequency divider, where the multi-phase clock signal is delayed by a preset period less than its cycle period, allowing for fractional frequency division to reduce noise, and additional adjustments are made using phase detectors and delayers to optimize delay times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple output clocks of the same frequency are generated and subjected to frequency division processing by a frequency divider, then the frequency divider can convert high-frequency signals into low-frequency signal outputs, but the output clock signal after frequency division processing has relatively large noise
Solution Approach 1:
The patent applies preliminary action by delaying the multi-phase clock signal by a preset period (less than one cycle period) before it enters the frequency divider. This pre-delay operation is performed by a phase selector that selects a specific channel from multiple phases and assigns the delay, preparing the signal in advance to reduce noise during subsequent frequency division processing.
Solution Approach 2:
The patent changes the timing parameter of the clock signal by introducing a preset period delay that is less than the full cycle period. This parameter modification allows the frequency divider to achieve fractional frequency division ratios, which fundamentally changes the noise characteristics of the output signal, reducing the noise to a fraction of its original level.
2Object-generated harmful factors
If a preset period delay is assigned to a clock signal of the selected channel, then the frequency divider can obtain a fractional frequency dividing ratio and reduce noise, but the device complexity increases due to additional phase selector and delay components
Solution Approach 1:
The phase selector is designed to perform multiple functions: it selects a specific channel from the multi-phase clock signal, assigns a preset period delay to the selected channel, and outputs the delayed signal to the frequency divider. By combining selection and delay functions in a single component, the patent reduces overall device complexity while achieving noise reduction.
Solution Approach 2:
The phase selector acts as an intermediary component between the phase generator and the frequency divider. It mediates the signal transmission by selecting and delaying the appropriate clock phase, enabling the frequency divider to achieve fractional division ratios without requiring complex internal modifications.
3Object-generated harmful factors
If fractional frequency division is performed on the delayed multi-phase clock signal, then the noise of the output low-frequency signal is reduced to a fraction of its original noise, but the manufacturing precision requirements increase for the phase selector and delay elements
Solution Approach 1:
The patent employs dynamic adjustment mechanisms in the phase selector and delay elements to compensate for manufacturing variations. The phase selector can dynamically select from multiple phases, and the delay elements can adjust their delay characteristics, allowing the system to achieve precise fractional frequency division ratios despite manufacturing tolerances.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor the output signal quality and adjust the phase selection and delay parameters accordingly. This feedback control ensures that the fractional frequency division achieves the desired noise reduction while compensating for any deviations in delay timing caused by manufacturing precision limitations.
Data Source
AI summary
The present disclosure discloses a clock signal noise reduction device and noise reduction method, and a multi-phase delay phase-locked loop. The clock signal noise reduction device includes a phase generator, a phase selector, and a frequency divider. The phase generator is configured to generate a multi-phase clock signal based on an input signal. The phase selector has an input end connected with an output end of the phase generator, and is configured to select a channel of the multi-phase clock signal based on phase information and assign a delay of a preset period to a clock signal of the selected channel. The preset period is less than a cycle period of the multi-phase clock signal. The frequency divider has an input end connected to an output end of the phase selector, and is configured to perform fractional frequency division on the multi-phase clock signal delayed by the preset period.