PLL Clock Glitch Detection Using Multi-Phase Oversampling
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Solution Overview
Problem
Contemporary electronic systems, such as data center devices and IoT devices, are vulnerable to hacking due to manipulation of the off-chip system clock, which can cause timing errors and glitches, allowing unauthorized access to protected data.
Innovation Solution
An on-die frequency-locked loop (FLL)-based or phase-locked loop (PLL)-based clock glitch detection device is employed to securely monitor the system clock, generating multiple local clocks and oversampling to detect glitches with high accuracy, reducing sensitivity to supply voltage variations and PVT corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an on-die FLL-based or PLL-based clock glitch detection device is employed to monitor the system clock, then clock glitch detection accuracy is improved, but device complexity increases
Solution Approach 1:
The detection device is segmented into distinct functional modules: an FLL/PLL circuit for frequency and phase locking, a sampling circuit for oversampling the system clock, a counter for measuring pulse widths, and a glitch detector for analyzing variations. This segmentation allows each module to perform its specific function efficiently while maintaining overall system manageability despite the increased complexity.
Solution Approach 2:
The FLL/PLL circuit acts as an intermediary between the system clock and the sampling circuit, providing a stabilized and multiplied clock signal. This intermediary component enables accurate measurement by converting the system clock into a form that is more suitable for precise sampling and analysis, thereby improving detection accuracy without directly increasing the complexity of the core detection logic.
2Measurement precision
If oversampling is used to detect glitches with high accuracy, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The sampling circuit performs oversampling at periodic intervals using multiple phases of local clocks generated by the FLL/PLL circuit. Instead of continuous monitoring, the system samples the system clock at discrete periodic moments, which reduces energy consumption while maintaining high detection accuracy through the accumulated statistical information from multiple samples.
Solution Approach 2:
The FLL/PLL circuit generates its own local clocks self-autonomously, which are then used by the sampling circuit for oversampling. This self-service mechanism eliminates the need for additional external clock sources, reducing the overall energy requirements of the system while enabling high-precision measurement through multiple phased sampling operations.
3Reliability
If multiple local clocks are generated for oversampling, then reliability is improved, but device complexity increases
Solution Approach 1:
The FLL/PLL circuit combines multiple clock generation functions into a single integrated component that produces multiple phases of local clocks simultaneously. This merging approach allows the sampling circuit to perform multi-phased oversampling using a unified clock generation mechanism, thereby improving reliability through redundant sampling paths while avoiding the complexity of separate clock generation circuits for each phase.
4Ease of operation
If the system uses off-chip system clock, then ease of operation is improved, but vulnerability to hacking increases
Solution Approach 1:
The on-die detection device performs preliminary monitoring and analysis of the system clock before it can be used by the rest of the system. By continuously sampling and analyzing clock signals in advance, the detection device can identify and respond to glitches or manipulations before they affect system operation, thereby maintaining ease of operation while preemptively countering hacking attempts.
Solution Approach 2:
The glitch detector provides feedback about the integrity of the system clock to the system, enabling real-time detection and response to clock manipulation attempts. This feedback mechanism allows the system to maintain simple operation using off-chip clocks while having an active monitoring layer that can detect and respond to security threats, effectively decoupling operational simplicity from security vulnerability.
Data Source
AI summary
A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.