PLL Clock Divider With Half-Integer Steps for Gap-Free Frequency Output
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Solution Overview
Problem
Conventional clock signal generation circuits are limited by the performance and complexity of voltage-controlled oscillators (VCOs) that operate at high frequencies or wide ranges, restricting the ability to generate output frequencies that are continuously programmable to lower frequencies without significant coverage gaps.
Innovation Solution
A clock signal generation circuit using a phase-locked loop with a frequency divider that allows for half-integer modulus steps, enabling the generation of output frequencies that are fractional submultiples by incorporating a first and second divider circuit connected in series, which divides the output signal by integer and half-integer values, reducing the required VCO operating range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a VCO operates at a high absolute operating frequency or over a wide frequency range, then the highest output frequency can be achieved, but the performance degrades and complexity increases
Solution Approach 1:
The frequency division function is segmented into two independent circuits: a first divider circuit that divides by integer values and a second divider circuit that divides by half-integer values. This segmentation allows the VCO to operate at a fixed, optimized frequency while the frequency division is handled by the segmented divider circuits, thereby reducing VCO complexity and improving performance.
2Speed
If a VCO operates at a high absolute operating frequency or over a wide frequency range, then the highest output frequency can be achieved, but performance degrades
Solution Approach 1:
The frequency division is segmented into integer division (first divider circuit) and half-integer division (second divider circuit). This allows the VCO to operate at a fixed, optimized frequency for best performance, while the segmented divider circuits handle the frequency multiplication to achieve various output frequencies, thereby maintaining high performance.
3Reliability
If the VCO frequency range is limited, then performance is improved, but the ability to generate continuously programmable output frequencies without coverage gaps is restricted
Solution Approach 1:
The divider system is segmented into a first divider circuit for integer division and a second divider circuit for half-integer division. This segmentation enables continuous frequency programming from the maximum output frequency down to one-quarter of the VCO frequency without coverage gaps, while the VCO itself can operate within a narrower, optimized frequency range for improved performance.
Solution Approach 2:
The invention extends the frequency division capability from a single dimension (integer steps) to two dimensions by introducing half-integer steps. This dimensional extension in the frequency division domain allows continuous frequency coverage while the VCO operates in a narrower, more efficient frequency range.
4Device complexity
If an integer divider is used, then the circuit is simple, but fractional submultiple frequencies cannot be generated
Solution Approach 1:
The frequency division function is segmented into two specialized circuits: a first divider circuit for integer division and a second divider circuit for half-integer division. This segmentation enables the generation of fractional submultiple frequencies (both integer and half-integer divisions) while keeping each individual divider circuit relatively simple in structure.
Data Source
AI summary
A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).