PLL Clock Multiplication to Avoid PMU Harmonic Channel Interference

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Solution Overview

Problem

Cellular phones experience communication interference due to noise coupling from the power management unit's harmonics, which exceed GSM noise boundaries, preventing communication on cellular networks.

Innovation Solution

Implementing a phase lock loop (PLL) to multiply the PMU clocking signal by a variable integer value, generating a PLL clock signal with a different frequency that avoids occupying the communication channel, thereby reducing interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the PMU is clocked using a frequency whose harmonics fall within the communication channel, then the PMU can operate efficiently, but it couples noise onto the communication channel causing interference

Engineering Contradiction:
ImprovePMU operating efficiencyVSAvoidnoise coupling onto communication channel
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the clocking frequency parameter of the PMU from a fixed frequency to a variable frequency that can be dynamically adjusted. The frequency is changed based on which communication channels are currently in use, so that the PMU clocking frequency and its harmonics never coincide with active communication channels, thereby eliminating noise coupling while maintaining efficient PMU operation

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements dynamic frequency adjustment of the PMU clocking signal. Instead of using a static clocking frequency, the system dynamically changes the PMU clocking frequency based on real-time communication channel usage. This dynamic adaptation allows the PMU to operate efficiently at different frequencies depending on which communication channels are active, preventing noise interference while maintaining productivity

Inventive Principle:
Principle #15Dynamics

2Device complexity

If the PMU operates at a fixed frequency, then the design is simple, but the harmonics may fall within communication channels causing interference

Engineering Contradiction:
ImprovePMU design simplicityVSAvoidharmonic interference with communication channel
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent transforms the PMU from using a fixed frequency to using a variable frequency that can be adjusted. This parameter change allows the system to avoid harmonic interference with communication channels while maintaining relatively simple design through the use of a phase-locked loop (PLL) frequency synthesizer and a lookup table for frequency selection

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If the PMU clocking frequency is adjusted to avoid communication channels, then noise coupling is reduced, but the system complexity increases

Engineering Contradiction:
Improvenoise coupling reductionVSAvoidfrequency adjustment mechanism
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent introduces a phase-locked loop (PLL) frequency synthesizer as an intermediary device between the communication channel usage detection and the PMU clocking. The PLL synthesizer, controlled by a lookup table, automatically generates the appropriate PMU clocking frequency based on which communication channels are in use. This intermediary mechanism handles the complexity of frequency adjustment, reducing noise coupling while managing system complexity through a dedicated frequency synthesis subsystem

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the use of previously degraded spectrum portions, reducing interference and allowing communication on GSM channels without degrading signal quality.

Implementation Method 1

a phase lock loop (PLL) to multiply the PMU clocking signal by a variable integer value, generating a PLL clock signal with a different frequency

Methodology Applied
Scientific EffectPhase lock loop frequency multiplication:

Data Source

PatentUS8954017B2Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device
Publication Date: 2015.02.10 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8954017B2 patent drawing
  • US8954017B2 patent drawing
  • US8954017B2 patent drawing

AI summary

A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.